Package systems and manufacturing methods thereof

• US 9,112,001 B2
• Filed: 02/05/2014
• Issued: 08/18/2015
• Est. Priority Date: 10/08/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shu, Chia-Pao, Cheng, Chun-wen, Chang, Kuei-Sung, Huang, Hsin-Ting, Peng, Jung-Huei, Tsai, Shang-Ying
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US14/173,406
• Publication Number:
  US 20140170849A1
• Time in Patent Office: 559 Days
• Field of Search: 438/455, 438/456, 257/618, 257/625, 257/688, 257/782, 257/783, 257/E21.122, 257/E23.01
• US Class Current: 1/1
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/0362 Photolithography
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05617 the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
• CPC Class Codes: H01L 2224/05638 the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/061 Disposition
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/26145 Flow barriers
• CPC Class Codes: H01L 2224/29011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/29014 being circular or elliptic
• CPC Class Codes: H01L 2224/29017 : being non uniform along the layer connector
• CPC Class Codes: H01L 2224/2902 : Disposition
• CPC Class Codes: H01L 2224/291 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29101 : the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/29117 : the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
• CPC Class Codes: H01L 2224/29124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29138 : the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29181 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/301 : Disposition
• CPC Class Codes: H01L 2224/32058 : being non uniform along the layer connector
• CPC Class Codes: H01L 2224/321 : Disposition
• CPC Class Codes: H01L 2224/32106 : the layer connector connecting one bonding area to at least two respective bonding areas
• CPC Class Codes: H01L 2224/32148 : the layer connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83365 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01037 : Rubidium [Rb]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS

Abstract

A method of forming a package system includes providing a first substrate having a metallic pad and at least one metallic guard ring. The method further includes bonding the metallic pad of the first substrate with a semiconductor pad of a second substrate, wherein the at least one metallic guard ring is configured to at least partially interact with the semiconductor pad to form at least a first portion of an electrical bonding material between the first and second substrates.

Claims

1. A method of forming a package system, the method comprising:

providing a first substrate having a metallic pad and at least one metallic guard ring, wherein the metallic pad protrudes above a top surface of the first substrate; and

bonding the metallic pad of the first substrate with a semiconductor pad of a second substrate, wherein the at least one metallic guard ring is configured to at least partially interact with the semiconductor pad to form at least a first portion of an electrical bonding material between the first and second substrates.

2. The method of claim 1, wherein the bonding process includes a eutectic bonding process.

3. The method of claim 1, wherein the first substrate includes at least one opening that is disposed between the metallic pad and the at least one metallic guard ring, and the bonding process pushes at least a portion of the electrical bonding material at least partially filling in the at least one opening.

4. The method of claim 3, wherein the bonding process comprises completely filling each opening of the at least one opening.

5. The method of claim 1, wherein the second substrate includes at least one semiconductor guard ring that is disposed around the semiconductor pad and the at least one semiconductor guard ring is configured to at least partially interact with at least one of the metallic pad and the at least one metallic guard ring to form at least a second portion of the electrical bonding material.

6. The method of claim 1, wherein bonding the metallic pad of the first substrate with the semiconductor pad of the second substrate comprises forming a non-hermetic package.

7. The method of claim 1, wherein providing the first substrate comprises:

depositing a first metal layer on the first substrate;

patterning the first metal layer to form the metallic pad;

depositing a second metal layer on the first substrate; and

patterning the second metal layer to form the at least one metallic guard ring.

8. The method of claim 7, wherein depositing the first metal layer comprises depositing the first metal layer using chemical vapor deposition (CVD) or physical vapor deposition (PVD), and depositing the second metal layer comprises depositing the second metal layer using CVD or PVD.

9. The method of claim 7, wherein patterning the first metal layer comprises etching the first metal layer, and patterning the second metal layer comprises etching the second metal layer.

10. A metal of forming a package system, the method comprising:

forming a metallic pad on a first substrate;

forming a metallic guard ring on the first substrate around the metallic pad;

forming an opening in the first substrate around the metallic pad; and

bonding the metallic pad and the metallic guard ring to a semiconductor material of a second substrate, wherein the bonding process comprises forming a eutectic bonding material between the first substrate and the second substrate, the eutectic bonding material includes the metallic pad and the metallic guard ring.

11. The method of claim 10, wherein forming the opening comprises etching the first substrate.

12. The method of claim 10, wherein forming the opening comprises:

forming a first opening in the first substrate; and

forming a second opening in the first substrate, wherein the first opening is connected to the second opening.

13. The method of claim 10, further comprising forming a second opening in the second substrate, wherein the second opening is closer to a center of the package system then the opening in the first substrate.

14. The method of claim 10, wherein the bonding process comprises at least partially filling the opening with the eutectic bonding material.

15. The method of claim 10, wherein the bonding process comprises forming a hermetic package system.

16. A method of forming a package system, the method comprising:

forming a plurality of first metallic pads on a first substrate;

forming a plurality of metallic guard rings on the first substrate, wherein each metallic guard ring of the plurality of metallic guard ring is around a corresponding first metallic pad of the plurality of first metallic pads;

forming a plurality of first openings in the first substrate, wherein each first opening of the plurality of first openings is around the corresponding first metallic pad of the plurality of first metallic pads;

forming a plurality of semiconductor pads on a second substrate; and

bonding each first metallic pad of the plurality of first metallic pad to a respective semiconductor pad of the plurality of semiconductor pads.

17. The method of claim 16, further comprising dicing the packaged system, wherein dicing the packaged system comprises sawing the packaged system between adjacent openings of the plurality of openings.

18. The method of claim 16, further comprising forming a plurality of second openings, wherein each second opening of the plurality of second openings is around a corresponding semiconductor pad of the plurality of semiconductor pads.

19. The method of claim 16, wherein the bonding process comprises at least partially filling each first opening of the plurality of first openings.

20. The method of claim 16, wherein the bonding process comprises reacting each semiconductor pad of the plurality of semiconductor pads with a respective first metallic pad of the plurality of first metallic pads.