Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit

• US 9,112,017 B2
• Filed: 08/15/2013
• Issued: 08/18/2015
• Est. Priority Date: 05/07/2010
• Status: Expired due to Fees

• Current Assignee: Power Integrations Incorporated
• Original Assignee: Power Integrations Incorporated
• Inventors: Banerjee, Sujit, Manley, Martin H.
• Primary Examiner(s): Nhu, David
• Application Number:
  US13/967,602
• Publication Number:
  US 20130328114A1
• Time in Patent Office: 733 Days
• Field of Search: 257/288, 257/350, 257/192, 257/322, 257/329, 257/339, 257/E21.051, 257/E21.315, 257/E21.325, 257/E21.435
• US Class Current: 1/1
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

A semiconductor device includes an N type well region in a P type substrate. A source region of a MOSFET is laterally separated from a boundary of the well region, which includes the drain of the MOSFET. An insulated gate of the MOSFET extends laterally from the source region to at least just past the boundary of the well region. A polysilicon layer, which forms a first plate of a capacitive anti-fuse, is insulated from an area of the well region, which forms the second plate of the anti-fuse. The anti-fuse is programmed by application of a voltage across the first and second capacitive plates sufficient to destroy at least a portion of the second dielectric layer, thereby electrically shorting the polysilicon layer to the drain of the HVFET.

Claims

1. A programmable power semiconductor device comprising:

a substrate of a first conductivity type;

a first well region of a second conductivity type disposed in the substrate, the second conductivity type being opposite to the first conductivity type;

a second well region of the first conductivity type disposed in the substrate, the second well region laterally adjoining the first well region at a boundary;

a first region of the second conductivity type disposed in the second well region, the first region being laterally separated from the boundary by a channel region, the first region comprising a source of a MOSFET;

a gate of the MOSFET disposed over the channel region, the gate being insulated from the channel region by a gate oxide that laterally extends from the first region to over a first area of the first well region adjacent the boundary;

a conductive layer disposed over a second area of the first well region, the conductive layer being insulated from the second area by a first dielectric layer, the conductive layer comprising a capacitive plate, the second area of the first well region comprising a drain of the MOSFET;

a second dielectric layer disposed over a third area of the first well region that laterally extends from the first dielectric layer to the gate oxide; and

a second region of the second conductivity type disposed in the first well region partially beneath the first dielectric layer and partially beneath the second dielectric layer.

2. The programmable power semiconductor device of claim 1 wherein the second region is disposed partially beneath a tapered edge of the second dielectric layer.

3. The programmable power semiconductor device of claim 1 wherein the first conductivity type is P-type and the second conductivity type is N-type.

4. The programmable power semiconductor device of claim 1 wherein the gate extends laterally over a portion of the second dielectric layer.

5. The programmable power semiconductor device of claim 1 wherein the second dielectric layer comprises a field oxide layer.

6. The programmable power semiconductor device of claim 1 wherein a lateral edge of the second region is aligned with a lateral edge of the conductive layer.

7. The programmable power semiconductor device of claim 1 wherein programming occurs by application of a first voltage on the gate sufficient to turn on the MOSFET, and a second voltage on the capacitive plate sufficient to short the capacitive plate to the drain of the MOSFET.

8. The programmable power semiconductor device of claim 1 wherein the second dielectric layer is substantially thicker than the first dielectric layer.

9. The programmable power semiconductor device of claim 1 further comprising a second region of the first conductivity type disposed in the second well region.

10. The programmable power semiconductor device of claim 6 wherein the second region of the first conductivity type laterally adjoins a side of the first region of the second conductivity type opposite the boundary.

11. The programmable power semiconductor device of claim 7 further comprising a source electrode electrically connected to the first region of the second conductivity type and to the second region of the first conductivity type.