Super junction structure having a thickness of first and second semiconductor regions which gradually changes from a transistor area into a termination area
First Claim
1. A super junction semiconductor device, comprising:
- a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction;
each one of the first areas includes a first semiconductor region of a first conductivity type;
each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type; and
whereina width w1 of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.
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Accused Products
Abstract
A super junction semiconductor device includes a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction. Each one of the first areas includes a first semiconductor region of a first conductivity type. Each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type. A width w1 of the first of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area.
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Citations
8 Claims
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1. A super junction semiconductor device, comprising:
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a super junction structure including first and second areas alternately arranged along a first lateral direction and extending in parallel along a second lateral direction;
each one of the first areas includes a first semiconductor region of a first conductivity type;
each one of the second areas includes, along the first lateral direction, an inner area between opposite second semiconductor regions of a second conductivity type opposite to the first conductivity type; and
whereina width w1 of the first semiconductor region in a transistor cell area is greater than in an edge termination area, and a width w2 of each one of the second semiconductor regions in the transistor cell area is greater than in the edge termination area. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification