Strained transistor integration for CMOS

• US 9,112,029 B2
• Filed: 05/02/2014
• Issued: 08/18/2015
• Est. Priority Date: 12/23/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Boyanov, Boyan, Murthy, Anand S., Doyle, Brian S., Chau, Robert S.
• Primary Examiner(s): Matthews, Colleen A
• Assistant Examiner(s): JEFFERSON, QUOVAUNDA
• Application Number:
  US14/268,938
• Publication Number:
  US 20140239345A1
• Time in Patent Office: 473 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Claims

1. An apparatus comprising:

a first layer of a silicon material suitable as a first channel for a first circuit device on a first interface surface of a first silicon alloy material;

wherein a lattice spacing of the silicon material is smaller than a lattice spacing of the first silicon alloy material at the first interface surface;

a second layer of a second silicon alloy material suitable as a second channel for a second circuit device on a second interface surface of the first silicon alloy material;

wherein a lattice spacing of the second silicon alloy material is larger than a lattice spacing of the first silicon alloy material at the second interface surface, wherein the second silicon alloy material has between 10 and 30 percent more Germanium than the first silicon alloy material, wherein the first silicon alloy material is a substrate of graded relaxed silicon Germanium material; and

wherein the graded relaxed silicon Germanium material has one of (1) a thickness of between 1 micrometer and 3 micrometers in thickness, and a grading concentration of Germanium that increases from 0 percent to between 10 percent and 30 percent at the first and second interface surfaces, or (2) a grading concentration rate that increases at between 5 percent Ge and 15 percent Ge per micrometer in a direction towards the first and second interface surfaces; and

a gate dielectric layer in contact with the Silicon material and the second Silicon alloy material.

2. The apparatus of claim 1, wherein the first silicon alloy material comprises Germanium in an amount of between 10 and 30 percent Germanium;

wherein the second silicon alloy material comprises Germanium in an amount of between 20 and 60 percent Germanium; and

wherein the first silicon alloy material has a lower percent of Germanium than the second silicon alloy material.

3. The apparatus of claim 1, wherein the first layer of a silicon material is a selectively grown material and is on a first area of the first interface surface;

and wherein the second layer of a second silicon alloy material is a selectively grown material and is on a second area of the second interface surface.

4. The apparatus of claim 3, wherein the layer of silicon material is an epitaxial layer of silicon material having a thickness of between 10 nano-meters and 20 nano-meters in thickness;

and wherein the layer of second silicon alloy material is an epitaxial layer of second silicon alloy material having a thickness of between 10 nano-meters and 20 nano-meters in thickness.

5. The apparatus of claim 1, wherein the gate dielectric layer is formed of one of silicon dioxide (SiO₂), hafnium oxide (HfO), hafnium silicate (HfSiO₄), hafnium disilicate (HfSi₄O₇), zirconium oxide (ZrO), zirconium silicate (ZrSiO₄), or tantalum oxide (Ta₂O₅).

6. The apparatus of claim 1, further comprising an electronically insulating material between the first area and the second area;

the first silicon alloy material doped at the first area with one of boron or aluminum to form a P-type well region having an electrically positive charge; and

the first silicon alloy material doped at the second area with one of phosphorous, arsenic, or antimony to form an N-type well region having an electrically negative charge.

7. The apparatus of claim 6, further comprising:

the first layer doped with one of boron and aluminum to form a P-type channel region having an electrically positive charge;

the second layer doped with one of phosphorous, arsenic, and antimony to form an N-type channel region having an electrically negative charge;

an N-type gate electrode on a surface of the gate dielectric layer over the first layer;

an N-type first junction region and an N-type second junction region in the first layer adjacent the N-type gate electrode;

wherein the gate electrode is a P-type gate electrode on a surface of the gate dielectric layer over the second layer; and

a P-type first junction region and an P-type second junction region in the second layer adjacent the P-type gate electrode.

8. An apparatus comprising:

a selectively grown layer of a silicon material suitable as a channel for a circuit device on an area of a first silicon alloy material defining an interface surface of a single layer of graded relaxed silicon Germanium material, wherein the layer of silicon material is an epitaxial layer of silicon material having a thickness of between 10 nano-meters and 20 nano-meters in thickness, wherein the graded relaxed silicon Germanium material has one of (1) a thickness of between 1 micrometer and 3 micrometers in thickness, (2) a grading concentration of Germanium that increases from 0 percent to between 10 percent and 30 percent at the interface surface, or (3) a grading concentration rate that increases at between 5 percent Ge and 15 percent Ge per micrometer in a direction towards the interface surface;

wherein a lattice spacing of the silicon material is smaller than a lattice spacing of the first silicon alloy material at the interface surface; and

a gate dielectric layer in contact with the selectively grown Silicon material.

9. The apparatus of claim 8, wherein the first silicon alloy material comprises Germanium in an amount of between 10 and 30 percent Germanium.

10. The apparatus of claim 8, wherein the gate dielectric layer is foamed of one of hafnium oxide (HfO), hafnium silicate (HfSiO₄), hafnium disilicate (HfSi₄O₇), zirconium oxide (ZrO), zirconium silicate (ZrSiO₄), or tantalum oxide (Ta₂O₅).

11. The apparatus of claim 8, further comprising an electronically insulating material beside the area;

the single layer material doped at the area with one of boron and aluminum to form a P-type well region having an electrically positive charge;

the layer of material doped with one of boron and aluminum to form a P-type channel region having an electrically positive charge;

an N-type gate electrode on a surface of the gate dielectric layer over the layer of silicon material; and

an N-type first junction region and an N-type second junction region in the layer of silicon material adjacent the N-type gate electrode.

12. An apparatus comprising:

a selectively grown layer of a second silicon alloy material suitable as a channel for a circuit device on an area of a first silicon alloy material defining an interface surface of a substrate of graded relaxed silicon Germanium material, wherein the layer of second silicon alloy material is an epitaxial layer of second silicon alloy material having a thickness of between 10 nano-meters and 20 nano-meters in thickness, wherein the graded relaxed silicon Germanium material has one of (1) a thickness of between 1 micrometer and 3 micrometers in thickness, (2) a grading concentration of Germanium that increases from 0 percent to between 10 percent and 30 percent at the interface surface, or (3) a grading concentration rate that increases at between 5 percent Ge and 15 percent Ge per micrometer in a direction towards the interface surface;

wherein a lattice spacing of the second silicon alloy material is larger than a lattice spacing of the first silicon alloy material at the interface surface, wherein the second silicon alloy material has between 10 and 30% more germanium than the first silicon alloy material; and

a gate dielectric layer in contact with the selectively grown second Silicon alloy material.

13. The apparatus of claim 12, wherein the second silicon alloy material comprises Germanium in an amount of between 20 and 60 percent Germanium;

and wherein the first silicon alloy material has a lower percent of Germanium than the second silicon alloy material.

14. The apparatus of claim 12, wherein the gate dielectric layer is formed of one of hafnium oxide (HfO), hafnium silicate (HfSiO₄), hafnium disilicate (HfSi₄O₇), zirconium oxide (ZrO), zirconium silicate (ZrSiO₄), or tantalum oxide (Ta₂O₅).

15. The apparatus of claim 12, wherein the first silicon alloy material comprises Germanium in an amount of between 10 and 30 percent Germanium.

16. The apparatus of claim 12, further comprising an electronically insulating material beside the area;

the substrate doped at the area with one of phosphorous, arsenic, and antimony to form an N-type well region having an electrically negative charge;

a P-type gate electrode on a surface of the gate dielectric layer over the layer of second silicon alloy material; and

a P-type first junction region and an P-type second junction region in the layer of second silicon alloy material adjacent the P-type gate electrode.

17. An apparatus comprising:

a selectively grown layer of a silicon material suitable as a first channel for a first circuit device on a first area of a first silicon alloy material defining a first interface surface of a single layer of graded relaxed silicon Germanium material;

wherein a lattice spacing of the silicon material is smaller than a lattice spacing of the first silicon alloy material at the first interface surface; and

wherein the graded relaxed silicon Germanium material has one of (1) a thickness of between 1 micrometer and 3 micrometers in thickness, (2) a grading concentration of Germanium that increases from 0 percent to between 10 percent and 30 percent at the first interface surface, or (3) a grading concentration rate that increases at between 5 percent Ge and 15 percent Ge per micrometer in a direction towards the first interface surface.

18. The apparatus of claim 17, wherein the first silicon alloy material comprises Germanium in an amount of between 10 and 30 percent Germanium.

19. The apparatus of claim 17, further comprising a gate dielectric on the layer of silicon material wherein the gate dielectric layer is formed of one of silicon dioxide (SiO₂), hafnium oxide (HfO), hafnium silicate (HfSiO₄), hafnium disilicate (HfSi₄O₇), zirconium oxide (ZrO), zirconium silicate (ZrSiO₄), or tantalum oxide (Ta₂O₅).