Integrated circuit process and bias monitors and related methods

• US 9,112,484 B1
• Filed: 12/20/2013
• Issued: 08/18/2015
• Est. Priority Date: 12/20/2012
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Clark, Lawrence T., Kidd, David A., Chen, Chao-Wu
• Primary Examiner(s): Johnson, Ryan
• Application Number:
  US14/136,258
• Time in Patent Office: 606 Days
• Field of Search: 331/57, 331/44
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor.

Claims

1. An integrated circuit device, comprising:

at least one oscillator stage that includes

a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths,

at least one reference transistor of a second conductivity type having a source-drain path coupled to a first of the mirror paths, and

a switching circuit coupled to a second of the mirror paths and configured to generate a transition in a stage output signal in response to a stage input signal received from another oscillator stage, wherein

the channel lengths of the first and second mirror transistors are larger than that of the at least one reference transistor;

wherein

the at least one oscillator stage includes a plurality of oscillator stages connected as ring oscillator circuit, with stage output signals of each oscillator stage being coupled to an input of another oscillator stage; and

body bias circuits configured to generate at least one body bias voltage in response to the ring oscillator circuit and apply the at least one body bias voltage to a group of transistors on the integrated circuit different from those of the ring oscillator circuit and monitor circuit.

2. The integrated circuit device of claim 1, wherein:

the channel length of the mirror transistors is no less than two times that of the at least one reference transistor.

3. The integrated circuit of claim 1, wherein:

the first and second mirror transistors have sources coupled to a first power supply node; and

the switching circuit includes

a first switching transistor of the first conductivity type having a source-drain path coupled to the source-drain path of the second current mirror transistor,

a second switching transistor of the second conductivity type having a source-drain path coupled between the first switching transistor and a second power supply node, and

a third switching transistor of the second conductivity type having a source-drain path coupled between the second switching transistor and the second power supply node.

4. The integrated circuit of claim 1, wherein:

the first and second mirror transistors have sources coupled to a first power supply node;

the switching circuit is coupled between the current mirror circuit and a second power supply node; and

the reference transistor is coupled to receive a body bias voltage that differs from a voltage received at the second power supply node.

5. The integrated circuit claim 1, wherein:

the first and second mirror transistors have sources coupled to a first power supply node;

the switching circuit is coupled between the current mirror circuit and a second power supply node; and

the reference transistor has a body coupled to the second power supply node.

6. The integrated circuit claim 1, wherein:

at least one oscillator stage further includes

the first and second mirror transistors have sources coupled to a first power supply node and commonly connected gates, and

a disable circuit comprising a disable transistor having a source-drain path in series with the reference transistor that is turned off in response to an enable signal.

7. The integrated circuit claim 1, wherein:

at least one oscillator stage further includes

the first and second mirror transistors have sources coupled to a first power supply node and commonly connected gates, and

a disable circuit configured to couple gates of the mirror transistors to the first power supply node in response to an enable signal.

8. The integrated circuit claim 1, further including:

a monitor circuit configured to generate a performance value based on an oscillator signal generated by the ring oscillator.

9. An integrated circuit, comprising:

at least one oscillator stage comprising,

a current mirror circuit comprising mirror transistors of a first conductivity type configured to mirror current drawn through a reference node at a mirror node;

at least one reference transistor of a second conductivity type having a drain coupled to a switching circuit configured to generate at least one stage output signal in response to at least one stage input signal, the switching circuit including,

a first switching transistor with a source coupled to the mirror node and a gate coupled to a stage input, and

a second switching transistor with a source-drain path in series with the source drain path of the first switching transistor, and a gate coupled to the stage input;

wherein

the stage input is coupled to receive the at least one input signal from another stage of the oscillator;

wherein

the at least one oscillator stage is operable in

an active mode in which a signal propagates through the switching circuit according to a current flowing through the reference transistor, and

an inactive mode in which substantially no current flows through the reference transistor and switching circuit.

10. The integrated circuit of claim 9, wherein:

the mirror transistors include

a first mirror transistor having a source coupled to a first power supply node and a gate and drain coupled to the reference node,

a second mirror transistor having a source coupled to the first power supply node and a gate coupled to the reference node, and a drain coupled to the mirror node; and

the reference transistor has a gate coupled to receive an enable signal and a source coupled to a second power supply node.

11. The integrated circuit of claim 9, wherein:

the switching circuit further includes a third switching transistor of the second conductivity type having a source-drain path coupled between that of the first switching transistor and that of the second switching transistor, and a gate coupled to the stage input.

12. The integrated circuit of claim 9, wherein:

the switching circuit includes

the first switching transistor having its gate coupled to receive a first stage output signal from another oscillator stage, and

the second switching transistor having its gate coupled to receive a second stage output signal from another oscillator stage.

13. The integrated circuit of claim 9, wherein:

the at least one oscillator stage further includes a disable transistor selected from;

a series disable transistor having a source-drain path in series with that of the reference transistor that is turned off in the inactive mode; and

a mirror disable transistor having a source-drain path coupled between a first power supply node and the gates of the mirror transistors that is enabled in the inactive mode.

14. A method, comprising:

in a stage of a ring oscillator circuit,

mirroring a reference current flowing through a reference transistor with a current mirror circuit to generate a mirrored current, the current mirror circuit comprising mirror transistors of a first conductivity type having channels lengths substantially larger than that of the reference transistor, and

controlling transitions in a stage output signal in response to a stage input signal with a switching circuit according to the mirrored current, wherein

the stage input signal is a stage output signal of another stage of the ring oscillator circuit

generating a body bias in response to an oscillating signal generated by the ring oscillator circuit; and

applying the body bias to transistors of an integrated circuit that includes the ring oscillator circuit.

15. The method of claim 14, wherein:

the mirror transistors have channel lengths no less than twice that of the reference transistor and channel widths no less than twice that of the reference transistor.

16. The method of claim 14, further including:

disabling the stage of the ring oscillator circuit by disabling a flow of the reference current.