Integrated circuit device body bias circuits and methods

• US 9,112,495 B1
• Filed: 03/15/2013
• Issued: 08/18/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Clark, Lawrence T., Kidd, David A., Kuo, Augustine
• Primary Examiner(s): Hiltunen, Thomas J
• Application Number:
  US13/838,221
• Time in Patent Office: 886 Days
• Field of Search: 327/534, 327/535, 327/537
• US Class Current: 1/1
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: H01L 27/0222 Charge pumping, substrate bias generation structures
• CPC Class Codes: H01L 27/0928 comprising both N- and P- wells in the substrate, e.g. twin-tub
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H02M 3/076 the clock signals being boosted to a value being higher than the input voltage value
• CPC Class Codes: H02M 3/078 with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to the first wells; and a first bias circuit corresponding to each first well and configured to generate a first local body bias for its well having a smaller setting voltage than the first global body bias voltage; wherein at least one of the first wells is coupled to a transistor having a strong body coefficient formed therein, which transistor may be a transistor having a highly doped region formed below a substantially undoped channel, the highly doped region having a dopant concentration greater than that the corresponding well.

Claims

1. A system, comprising:

a plurality of blocks, each block comprising a different integrated circuit function and each including transistors formed therein;

a bias circuit corresponding to each block and configured to receive a control value unique to the block, each bias circuit configured to generate a local body bias voltage for transistors of its block in response to the control value of the block;

a collapse circuit corresponding to each block, each collapse circuit configured to couple the bodies of its transistors to a collapse voltage that tracks a power supply voltage, in response to at least one collapse enable signal for the block; and

an event detect circuit corresponding to each block, each event detect circuit configured to activate the collapse enable signal of its block in response to at least one local event signal and in response to at least one global event signal;

wherein

the at least one local event signal is generated in the corresponding block and the at least one global event signal is generated outside of the block in response to at least one predetermined event.

2. The system of claim 1, wherein:

the blocks include a processor circuit block comprising at least one processor and a static or dynamic RAM block; and

the local body bias voltage for transistors of the processor block is different from the local body bias voltage for transistors of the memory block.

3. The system of claim 1, wherein:

each bias circuit receives a multi-bit control value and includes a digital to analog converter (DAC) that converts the control value into an analog value.

4. The system of claim 3, wherein:

the DAC of each bias circuit generates a control voltage for the bias circuit that establishes the local body bias voltage.

5. The system of claim 1, wherein:

each bias circuit includes a bias transistor having a source-drain path coupled between bodies of the transistors of its block and a global body bias voltage; and

each collapse circuit includes a collapse transistor having a source-drain path coupled between bodies of the transistors of its block and the collapse voltage.

6. The system of claim 1, wherein:

the bias circuits include

n-channel body bias circuits that generate a local body bias for n-channel transistors of its block, and

p-channel body bias circuits that generate a local body bias for p-channel transistors of its block; and

the collapse circuits include

n-channel collapse circuits configured to couple bodies of n-channel transistors of its block to a first collapse voltage, and

p-channel collapse circuits configured to couple bodies of p-channel transistors of its block to a second collapse voltage.

7. The system of claim 1, wherein:

the transistors include deeply depleted channel (DDC) transistors formed therein, each DDC transistor comprising a body which includes a screening region formed below a substantially undoped channel, the screening region having a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³.

8. The system of claim 1, wherein:

the at least one predetermined event is a current transient generating event on an IC device containing the blocks.

9. The system of claim 1, wherein:

the predetermined event is selected from the group of;

an interrupt generated by a processor of the IC device;

a command received from a source external to the IC device; and

a power up of an IC device containing the blocks.

10. A method, comprising:

generating different local body bias voltages from a global body bias voltage;

applying each local body bias voltage to transistors of different blocks in an integrated circuit (IC) device, each block comprising a different integrated circuit function, the transistors including deeply depleted channel (DDC) transistors; and

in response to at least one local event and in response to a global event, coupling bodies of the transistors of a block to a collapse voltage that tracks a power supply voltage;

wherein

each DDC transistor comprises a body with a screening region of a dopant concentration of no less than 1×

10¹⁸ dopant atoms/cm³ formed below a transistor channel, and

the at least one local event occur on the block and not another block, the global event occurs outside of the block.

11. The method of claim 10, wherein:

at least one of the transistors operates in the subthreshold region.

12. The method of claim 11, wherein:

at least one of the transistors operates having a threshold voltage setting that is less than or equal to 0.2V less than the supply voltage to such transistor.

13. The method of claim 10, wherein:

generating different local body bias voltages includes DC-DC converting the common global body bias voltage to a smaller setting local body bias voltage.

14. The method of claim 10, wherein:

generating different local body bias voltages setting the local body bias voltage according to a digital control value.

15. The method of claim 10, wherein:

each local body bias voltage is applied to at least one well formed in a semiconductor substrate; and

generating different local body bias voltages includes controlling the impedance of a path between the global body bias voltage and the well in response to a difference between a reference voltage and a voltage of the well.

16. The method of claim 10, wherein:

each local body bias voltage is applied to at least one well formed in a semiconductor substrate; and

generating different local body bias voltages includes switching an impedance path on and off in response to a difference between a reference voltage and a voltage of the well, the impedance path being formed between the global body bias voltage and the well.

17. The method of claim 10, further including:

generating the global body bias voltage from a high power supply voltage with generating circuits on the IC device; and

applying a low power supply voltage to low power circuits of the IC device only after the high power supply voltage has been generated and the local body bias voltages are stable.

18. The method of claim 17, further including:

generating the global body bias voltage includes generating a negative global body bias voltage for n-channel transistors with a charge pump.

19. The method of claim 10, wherein:

the collapse voltage is selected from the group of;

a high power supply voltage, a low power supply voltage, a voltage that is less than a high power supply voltage, and a voltage that is greater than a low power supply voltage.

20. The method of claim 10, wherein:

the at least one global event is selected from the group of;

an interrupt generated by a processor of the IC device; and

a command received from a source external to the IC device.

21. The method of claim 10, wherein:

applying each local body bias voltage includes

applying a first local body bias voltage to transistors in one block having a first threshold voltage, and

applying a second local body bias voltage to transistors in another block having a second threshold voltage different than the first threshold voltage.