Phase-locked loop start up circuit

• US 9,112,507 B2
• Filed: 03/09/2010
• Issued: 08/18/2015
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chien-Hung, Tsai, Tsung-Hsien, Chou, Mao-Hsuan
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): O TOOLE, COLLEEN J
• Application Number:
  US12/719,951
• Publication Number:
  US 20110221494A1
• Time in Patent Office: 1,988 Days
• Field of Search: 327/141, 327/144, 327147-150, 327156-159, 375373-376, 331/16, 331/17
• US Class Current: 1/1
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H03L 7/101 using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop H03L7/113, H03L7/187 take precedence

Abstract

A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.

Claims

1. A phase-locked loop (PLL) circuit, comprising:

a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output;

a feedback loop between the VCO input and the VCO output; and

a start-up circuit having a start-up circuit input and a start-up circuit output, wherein the start-up circuit output is coupled to the VCO input and wherein the start-up circuit input is coupled to the VCO output,

wherein the start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.

2. The PLL circuit of claim 1, wherein the start-up circuit comprises a cycle counter.

3. The PLL circuit of claim 2, wherein the cycle counter counts feedback pulses received at the start-up circuit input, wherein the start-up circuit provides a start-up voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the cycle counter.

4. The PLL circuit of claim 3, wherein the predetermined number of feedback pulses is between 2 to 8 feedback pulses.

5. The PLL circuit of claim 3, wherein the predetermined number of feedback pulses is 4 feedback pulses.

6. The PLL circuit of claim 1, wherein the feedback loop comprises a loop filter coupled to the VCO input.

7. The PLL circuit of claim 6, wherein the feedback loop further comprises:

a phase frequency detector having a first input for receiving a signal having an input frequency, a second input and an output;

a pump having an input coupled to the output of the phase frequency detector and an output coupled to the loop filter; and

a feedback divider having an input coupled to the VCO output and an output coupled to the second input of the phase frequency detector.

8. The PLL circuit of claim 7, wherein the output of the feedback divider is coupled to the start-up circuit input.

9. A phase-locked loop (PLL) circuit, comprising:

a voltage-controlled oscillator (VCO) having a VCO input coupled to a voltage control node and a VCO output;

a loop filter coupled to the voltage control node;

a phase frequency detector having a first input for receiving a signal having an input frequency, a second input and an output;

a pump having an input coupled to the output of the phase frequency detector and an output coupled to the loop filter;

a feedback divider having an input coupled to the VCO output and an output coupled to the second input of the phase frequency detector; and

a start-up circuit having a start-up circuit input coupled to the output of the feedback divider and a start-up circuit output coupled to the voltage control node.

10. The PLL circuit of claim 9, wherein the start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit.

11. The PLL circuit of claim 9, wherein the start-up circuit comprises:

a cycle counter, wherein the cycle counter counts feedback pulses received at the start-up circuit; and

a voltage source, said voltage source providing a pulling voltage to the voltage control node during a start-up phase.

12. The PLL circuit of claim 11, wherein the start-up phase terminates after a predetermined number of feedback pulses are detected by the cycle counter.

13. The PLL circuit of claim 12, wherein the predetermined number of feedback pulses is between 2 to 8 feedback pulses.

14. The PLL circuit of claim 12, wherein the predetermined number of feedback pulses is 4 feedback pulses.

15. The PLL circuit of claim 12, wherein the cycle counter is a binary counter.

16. The PLL circuit of claim 12, wherein the predetermined number of feedback pulses is selected so that the start-up phase terminates before a target frequency for the phase-locked loop circuit is reached.

17. The PLL circuit of claim 10, wherein the loop filter comprises at least one capacitor.

18. A phase-locked loop (PLL) circuit, comprising:

a voltage-controlled oscillator (VCO) having a VCO input coupled to a voltage control node and a VCO output;

a loop filter coupled to the voltage control node, the loop filter comprising at least one capacitor;

a phase frequency detector having a first input for receiving a signal having an input frequency, a second input and an output;

a pump having an input coupled to the output of the phase frequency detector and an output coupled to the loop filter;

a feedback divider having an input coupled to the VCO output and an output coupled to the second input of the phase frequency detector; and

a start-up circuit having a start-up circuit input coupled to the output of the feedback divider and a start-up circuit output coupled to the voltage control node, wherein the start-up circuit outputs a pulling voltage for charging the at least one capacitor of the loop filter during a start-up phase,

wherein the start-up circuit includes a detector for detecting feedback pulses from the phase-frequency detector and terminating the start-up phase after detection of a predetermined number of feedback pulses, and

wherein the predetermined number of feedback pulses is selected so that the start-up phase terminates before a target frequency for the phase-locked loop circuit is reached.

19. The PLL circuit of claim 18,

wherein the detector of the start-up circuit comprises a cycle counter, and

wherein the start-up circuit comprises a voltage source under control of the cycle counter for providing the pulling voltage during the start-up phase.

20. The PLL circuit of claim 18, wherein the predetermined number of feedback pulses is 4.