Geographic locating remote endpoint monitor device, system, and methodology thereof

• US 9,112,515 B2
• Filed: 07/11/2014
• Issued: 08/18/2015
• Est. Priority Date: 03/30/2001
• Status: Expired due to Fees

• Current Assignee: Sensus Spectrum, LLC (Xylem, Inc.)
• Original Assignee: Sensus Spectrum, LLC (Xylem, Inc.)
• Inventors: Sanderford, H. Britton Jr., Rouquette, Robert E., Naden, Gary A., Reed, Marc L., Boudreaux, Gordon J., Brown, Michael R.
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US14/329,333
• Publication Number:
  US 20140320182A1
• Time in Patent Office: 403 Days
• Field of Search: 375/238, 375/327, 375/372, 375/373, 375/375, 375/376, 327/147, 327/150, 327/151, 327/156, 327/159, 327/160
• US Class Current: 1/1
• CPC Class Codes: H03B 21/00 Generation of oscillations by combining unmodulated signals of different frequencies H03B19/00 takes precedence; frequency changing circuits in general H03D
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation
• CPC Class Codes: H04L 25/4921 using quadrature encoding, e.g. carrierless amplitude-phase coding
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/2331 wherein the received signal is demodulated using one or more delayed versions of itself
• CPC Class Codes: H04L 27/32 Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
• CPC Class Codes: H04L 27/34 Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
• CPC Class Codes: H04L 27/3433 using an underlying square constellation
• CPC Class Codes: H04L 27/3483 using a modulation of the constellation points
• CPC Class Codes: H04L 27/364 Arrangements for overcoming imperfections in the modulator, e.g. quadrature error or unbalanced I and Q levels
• CPC Class Codes: H04L 27/38 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/3845 using non - coherent demodulation, i.e. not using a phase synchronous carrier
• CPC Class Codes: H04L 5/06 the signals being represented by different frequencies combined with time-division multiplexing H04L5/26
• CPC Class Codes: H04L 5/16 Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission
• CPC Class Codes: H04W 36/08 Reselecting an access point
• CPC Class Codes: H04W 36/083 wherein at least one of the access points is a moving node
• CPC Class Codes: H04W 72/27 between access points

Abstract

A phase-locked loop frequency synthesizer includes an L-state pulse width modulator configured to receive a reference frequency signal and at least one entry from a frequency table, and to output at least one N/N+1 modulus signals corresponding to the at least one entry from the frequency table. The synthesizer includes a divide by N/N+1 controllable modulus divider configured to receive the at least one N/N+1 modulus signals and to divide the output frequency signal by the at least one N/N+1 modulus signals to generate a second reference frequency signal. The synthesizer includes a phase frequency detector configured to receive the reference frequency signal and the second reference frequency signal and to generate an error signal. The synthesizer also includes a filter network configured to receive the error signal and to output a voltage; and a voltage controlled oscillator configured to receive the voltage and to generate the output frequency signal.

Claims

1. A phase-locked loop frequency synthesizer, comprising:

a pulse width modulator configured to receive a reference frequency signal and at least one entry from a frequency table, and to output N/N+1 modulus signals corresponding to the at least one entry from the frequency table, wherein N is a divider modulus;

a divide by N/N+1 controllable modulus divider configured to receive the N/N+1 modulus signals and to divide an output frequency signal by the N/N+1 modulus signals to generate a second reference frequency signal;

a phase frequency detector configured to receive the reference frequency signal and the second reference frequency signal and to generate an error signal;

a filter network configured to receive the error signal and to output a voltage; and

a voltage controlled oscillator configured to receive the voltage and to generate the output frequency signal.

2. The phase-locked loop frequency synthesizer of claim 1, wherein:

the filter network comprises at least one notch filter between the phase frequency detector and the voltage controlled oscillator.

3. The phase-locked loop frequency synthesizer of claim 2, wherein the at least one notch filter comprises a twin-T RC passive filter.

4. The phase-locked loop frequency synthesizer of claim 2, wherein the at least one notch filter comprises a twin-T RC active filter.

5. The phase-locked loop frequency synthesizer of claim 1, wherein:

the pulse width modulator includes 68 states,

N is 64, and

the frequency table is configured to store entries having values of 0 to 68.