Network interface and protocol

• US 9,112,752 B2
• Filed: 10/22/2010
• Issued: 08/18/2015
• Est. Priority Date: 09/16/2002
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: SolarFlare Communications Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Pope, Steve Leslie, Roberts, Derek Edward, Riddoch, David James, Clarke, David Julian
• Primary Examiner(s): SISON, JUNE Y
• Application Number:
  US12/910,391
• Publication Number:
  US 20110040897A1
• Time in Patent Office: 1,761 Days
• Field of Search: 709/250
• US Class Current: 1/1
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/545 where tasks reside in different layers, e.g. user- and kernel-space
• CPC Class Codes: H04L 61/00 Network arrangements, protocols or services for addressing or naming
• CPC Class Codes: H04L 61/35 involving non-standard use of addresses for implementing network functionalities, e.g. coding subscription information within the address or functional addressing, i.e. assigning an address to a function

Abstract

A communication interface for providing an interface between a data link and a data processor, the data processor being capable of supporting an operating system and a user application, the communication interface being arranged to: support a first queue of data received over the link and addressed to a logical data port associated with a user application; support a second queue of data received over the link and identified as being directed to the operating system; and analyze data received over the link and identified as being directed to the operating system or the data port to determine whether that data meets one or more predefined criteria, and if it does meet the criteria transmit an interrupt to the operating system.

Claims

1. An apparatus comprising:

a communication interface for providing an interface between a data link and a data processor, the data processor being configured to support an operating system, a virtual address space and one or more logical data ports, the logical data ports existing within the operating system, the communication interface comprising at least one of a processor and circuitry to;

apply first data received over the link and addressed to one of said one or more logical data ports to a first queue associated with the said one logical data port, said first queue being located in the virtual address space,

analyse said first data to determine whether said first data meets one or more predefined criteria, wherein one of the predefined criteria is that the handling of said first data directed to said one logical data port is blocked,

determine, based on said analysis, that the handling of said first data directed to the said one logical data port is blocked, and

in response to determining that the handling of said first data directed to the said one logical data port is blocked, i) generate a message indicating the said one logical data port, ii) apply the message to a second queue located in the address space of the operating system and iii) transmit an interrupt to the operating system, said address space of said first queue being different to that of the second queue, and in response to determining that the handling of said first data directed to the said one logical data port is not blocked, handling the first data without the operating system.

2. The apparatus as claimed in claim 1, wherein one of the predefined criteria is that the data directed to the said one logical data port matches one or more predetermined message forms.

3. The apparatus as claimed in claim 1, wherein one of the predefined criteria is that the data is indicative of an error condition.

4. The apparatus as claimed in claim 1, wherein the communication interface is arranged to apply to a third queue data received over the link and addressed to the logical data port, and is arranged to apply to the first queue data units received over the link and of a form having a fixed length and to apply to the third queue data units received over the link and of a form having a variable length.

5. The apparatus as claimed in claim 4, wherein the data units of a fixed size include messages received over the link and interpreted by the communication interface as indicating an error status.

6. The apparatus as claimed in claim 4, wherein the data units of a fixed size include messages received over the link and interpreted by the communication interface as indicating a request for or acknowledgement of setup of a connection.

7. The apparatus as claimed in claim 5, wherein the data units of a fixed size include messages received over the link and interpreted by the communication interface as indicating a data delivery event.

8. The apparatus as claimed in claim 1, wherein the communication interface is arranged to analyse the content of each data unit received over the link and to determine in dependence on the content of that data unit which of the said queues to apply the data unit to.

9. The apparatus as claimed in claim 1, wherein the communication interface is configurable by the operating system to set the said criteria.

10. The apparatus as claimed in claim 1, wherein one or both of the communication interface and the operating system is responsive to a message of a predetermined type to return a message including information indicative of the status of the port.

11. A communication system including the apparatus of claim 1 and the data processor, the data processor to set the predefined criteria.

12. The apparatus as claimed in claim 1, wherein the communication interface is arranged to generate the message.

13. The apparatus as claimed in claim 1, wherein the communication interface is further arranged to:

apply to the second queue data for the particular logical data port and directed to the operating system, said data being indicative of an error condition.

14. The apparatus as claimed in claim 13, wherein said data applied to the second queue is received over the link or is generated by the communication interface.

15. A data processing system comprising:

a data processor; and

the apparatus of claim 1, wherein the particular logical data port exists within the operating system.

16. A data processing system as claimed in claim 15, wherein the operating system is arranged to analyse the message transmitted to the second queue so as to identify the port and examine the data applied to the first queue.

20. The apparatus of claim 1, wherein

said first data received over the link is out of band (OOB) data, and

said first queue is an OOB queue.

21. The apparatus of claim 20, wherein said OOB queue has a read pointer and a write pointer, said read pointer being stored in said virtual address space and said write pointer being stored in said communication interface.

17. A data processing system comprising:

an operating system;

a virtual address space;

a logical data port being associated with the virtual address space and existing within the operating system; and

a communication interface for providing an interface between a data link and the data processing system, the communication interface comprising at least one of a processor and circuitry to;

(i) apply data received over the link and addressed to the logical data port to a first queue associated with the logical data port and located in the virtual address space;

(ii) analyse the received data to determine whether the received data meets one or more predefined criteria wherein one of the predefined criteria is that the handling of data directed to the logical data port is blocked; and

in response to determining that the handling of data directed to the said one logical data port is blocked;

(iii) generate a message indicating the said one logical data port;

(iv) apply the message to a second queue located in the address space of the operating system; and

(v) transmit an interrupt to the operating system, wherein

said at least one of a processor and circuitry being further arranged to handle the first data without the operating system if the handling of said data directed to the said one logical data port is not blocked, and

said address space of the first queue being different to that of the second queue.

18. The data processing system of claim 17, wherein

said data received over the link is out of band (OOB) data, and

said first queue is an OOB queue.

19. The apparatus of claim 18, wherein said OOB queue has a read pointer and a write pointer, said read pointer being stored in said virtual address space and said write pointer being stored in said communication interface.

22. An apparatus comprising:

a communication interface for providing an interface between a data link and a data processor, the data processor being capable of supporting an operating system and a user application, the communication interface comprising at least one of a processor and circuitry to;

apply first out of band data received over the link and addressed to one of said one or more logical data ports to a first queue associated with the said one logical data port, said first queue being located in the address space of the user application, said first queue being an out of band queue;

determine if the handling of said first out of band data directed to the said one logical data port is blocked; and

in response to determining that the handling of said first data directed to the said one logical data port is blocked, generate a message indicating the said one logical data port, apply the message to a second queue located in the address space of the operating system and additionally transmit an interrupt to the operating system, said address space of said first out of band data queue being different to that of the second queue, and if the handling of the first data directed to the said one logical port is not blocked, handling the first data by the first application.