Test coverage of integrated circuits with test vector input spreading

• US 9,116,205 B2
• Filed: 09/27/2012
• Issued: 08/25/2015
• Est. Priority Date: 09/27/2012
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Douskey, Steven M., Fitch, Ryan A., Hamilton, Michael J., Kaufer, Amanda R.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Vallecillo, Kyle
• Application Number:
  US13/628,231
• Publication Number:
  US 20140089750A1
• Time in Patent Office: 1,062 Days
• Field of Search: 714/729, 714/30, 714/726, 702/117
• US Class Current: 1/1
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts

Abstract

An apparatus and method is provided for switching input pins to scan channels to increase test coverage. In one embodiment, a scan system connects a small number of input pins to several scan channels so that the input pins may be selectively switched. The input pins may transmit independent test vectors to test a large number of test areas on a semiconductor chip. The scan system may include a switching device such as a multiplexer (MUX).

Claims

1. A system, comprising:

a plurality of scan chains, each scan chain is configured to receive a test vector and apply the test vector;

a plurality of test vector sources to provide test vectors;

a plurality of switching devices, each switching device is electrically coupled to a scan chain from the plurality of scan chains and to at least two test vector sources from the plurality of test vector sources, and each switching device is configured to select a test vector source from the at least two test vector sources to be electrically coupled to the scan chain based on a test mode signal; and

a test mode signal source that provides a plurality of test mode signals to the plurality of switching devices,

wherein the test mode signal source is configured to implement the plurality of test mode signals so that a first schedule of test vector sources is electrically coupled to a first scan chain is different from a second schedule of test vector sources electrically coupled to a second scan chain throughout the plurality of test mode signals,

wherein the first schedule of test vector sources includes selection of a first test vector source in response to a first test mode signal, and selection of a second test vector source in response to a second test mode signal,

wherein the second schedule of test vector sources includes selection of the second test vector source in response to the first test mode signal, and selection of the first test vector source to the second scan chain in response to the second test mode signal,

wherein the first test mode signal from the plurality of test mode signals causes a first switching device to electrically couple the first test vector source from the first schedule of test vector sources to the first scan chain and, simultaneously, causes a second switching device to electrically couple the second test vector source from the second schedule of test vector sources to the second scan chain,

wherein the second test mode signal from the plurality of test mode signals causes the first switching device to electrically couple the second test vector source from the first schedule of test vector sources to the first scan chain and, simultaneously, causes the second switching device to electrically couple the first test vector source from the second schedule of test vector sources to the second scan chain,

wherein the second test vector source is different than the first test vector source,

wherein the first test mode signal for a first switching device from the plurality of switching devices is different within the same time domain from a second test mode signal for a second switching device from the plurality of switching devices.

2. The system of claim 1, wherein a number of the plurality of test vector sources is less than a number of the plurality of scan chains.

3. The system of claim 1, wherein at least one of the test vector sources is selectively inverted for every bit of the test vectors from the test vector source.

4. The system of claim 1, wherein no two test vector sources are electrically coupled at the same time to the scan chain throughout the plurality of test mode signals.

5. The system of claim 1, wherein the test mode signal source is configured to remove test mode signals that permit the first schedule of test vector sources electrically coupled to a first scan chain to be the same as the second schedule of test vector sources electrically coupled to a second scan chain.

6. A circuit, comprising:

a Scan Data In (SDI) that transmits a test vector;

a multiplexer having at least two or more inputs that are electrically coupled to the SDI and an output that electrically couples to a scan chain, wherein at least one of the inputs is inverted for every bit of the test vector, wherein the multiplexer has a selector that is selected by a test mode signal that causes the multiplexer to select between an inverted input or a non-inverted input to electrically couple to the scan chain; and

the scan chain that receives a test vector through the multiplexer.

7. The circuit of claim 6, further comprising:

a second scan chain that is electrically coupled to a second multiplexer; and

the second multiplexer having at least two or more inputs that are electrically coupled to the SDI, wherein at least one of the inputs is inverted for every bit of the test vector.

8. A circuit, comprising:

a plurality of Scan Data Ins (SDI) that transmit a plurality of test vectors, each SDI transmits a different test vector;

a multiplexer having at least three inputs, each input is electrically coupled to at least one SDI, and an output of the multiplexer is electrically coupled to a scan chain, wherein at least one of the inputs is inverted for every bit of the test vector, wherein the multiplexer is selected by a test mode signal that causes the multiplexer to select between an inverted input or a non-inverted input to electrically couple to the scan chain; and

the scan chain that receives the test vector from the plurality of test vectors through the multiplexer.