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IC gating selection on first/second and deselection on second/third counts

  • US 9,116,207 B2
  • Filed: 10/02/2014
  • Issued: 08/25/2015
  • Est. Priority Date: 07/29/2008
  • Status: Active Grant
First Claim
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1. An integrated circuit comprising:

  • A. a test clock lead capable of receiving a test clock signal;

    B. a test mode select counter lead capable of carrying bidirectional serial data signals and receiving a test mode select signal;

    C. first circuitry having inputs coupled to the test clock lead and to the test mode select counter lead, and having a CE clock output lead for carrying CE clock signals;

    D. counter circuitry having a CE clock input connected to the CE clock output lead, the counter circuitry counting edges of the CE clock signals, a first count output corresponding to a first count of the CE clock signals, a second count output corresponding to a second count of the CE clock signals, and a third count output corresponding to a third count of the CE clock signals; and

    E. gating circuitry having inputs connected to the first, second, and third count outputs and having a selection output lead carrying an output based on the first and second count outputs, and a deselection output lead carrying an output based on the second and third outputs.

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