Integrated circuit testing module including signal shaping interface

• US 9,116,210 B2
• Filed: 09/10/2012
• Issued: 08/25/2015
• Est. Priority Date: 09/28/2001
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ong, Adrian E.
• Primary Examiner(s): Tu, Christine
• Application Number:
  US13/609,019
• Publication Number:
  US 20130066581A1
• Time in Patent Office: 1,079 Days
• Field of Search: 714/738, 714/739, 714/744, 714/798, 714/724
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: G01R 31/31928 Formatter driver, receiver details G01R31/31924
• CPC Class Codes: G01R 31/3193 with comparison between actual response and known fault free response receiver details G01R31/31924
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
• CPC Class Codes: G06F 11/27 Built-in tests
• CPC Class Codes: G06F 11/2733 Test interface between tester and unit under test
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment.

Claims

1. An apparatus, comprising:

a first component to communicate at a first frequency, the first components comprising a receiving component to receive a test signal at the first frequency and to output information derived from the test signal;

a data generating component coupled to receive the information from the first component and to generate test data responsive to the information; and

a second component to transmit test data based on the information to at a second frequency different than the first frequency.

2. The apparatus of claim 1, wherein the apparatus is a test module.

3. The apparatus of claim 2, wherein the first component is to communicate with a test equipment and the second component is to transmit the test data to a device external to the apparatus.

4. The apparatus of claim 1, wherein the data generating component is programmable.

5. The apparatus of claim 1, wherein the first component comprises at least one of a clock manager, a command unit, a test control unit or a test data interface.

6. The apparatus of claim 1, wherein the data generating component to generate at least one of test codes, vectors or patterns as the test data.

7. The apparatus of claim 3, wherein the data generating component to generate a sequence of test and a series of data patterns associated with the test data to be sent to the device.

8. The apparatus of claim 1, wherein the data generating component comprises a clock manager to receive a test clock signal at the first frequency and a PLL clock, the clock manager to generate another clock signal at the second frequency.

9. The apparatus of claim 1, wherein the second component comprises at least one of a clock driver, a command driver, an address driver or a data interface.

10. A method, comprising:

receiving a first signal having a first frequency from a testing equipment;

generating a test signal based on the first signal; and

sending the test signal to an apparatus at a second frequency different than the first frequency.

11. The method of claim 10, wherein the first signal is configured to select a test plan from a test plan memory component.

12. The method of claim 11, wherein the apparatus is an integrated circuit and wherein the method further comprises changing the test plan based on results received from the integrated circuit in response to the test signal.

13. The method of claim 10, wherein generating the test signal is performed by a test module.

14. The method of claim 13, wherein the apparatus is a device different than the test module.

15. The method of claim 10, wherein the first signal is received by one of a clock manager, a command unit, a test control unit or a test data interface.

16. The method of claim 10, further comprising storing at least one of test codes, vectors or patterns as the test signal.

17. The method of claim 10, further comprising storing a series of data patterns associated with the test signal to be send to the apparatus.

18. The method of claim 10, wherein receiving the first signal having the first frequency is performed by a clock manager and wherein the method further comprises generating, by the clock manager, another clock signal at the second frequency.

19. The method of claim 10, wherein sending the test signal comprising sending the test signal by one of a clock driver, a command driver, an address driver or a data interface.