Maintaining synchronization during vertical blanking

• US 9,116,639 B2
• Filed: 12/18/2012
• Issued: 08/25/2015
• Est. Priority Date: 12/18/2012
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Tripathi, Brijesh
• Primary Examiner(s): Lee, Thomas
• Assistant Examiner(s): ERDMAN, CHAD G
• Application Number:
  US13/717,978
• Publication Number:
  US 20140173320A1
• Time in Patent Office: 980 Days
• Field of Search: 713/375
• US Class Current: 1/1
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 2370/047 using display data channel standard [DDC] communication
• CPC Class Codes: G09G 2370/10 Use of a protocol of communication by packets in interfaces along the display data pipeline
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, an auxiliary link, and a hot plug detect link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link. The source processor may send initialization parameters to the sink processor via the primary link. The initialization parameters may include a clock data recovery lock parameter and an idle parameter. Following the initialization parameters, the source processor may send a synchronization signal to the sink processor via the primary link. The source processor may then send a sleep command via the primary link to the sink processor.

Claims

1. An apparatus, comprising:

a source processor; and

a sink processor coupled to the source processor through a primary link and an auxiliary link;

wherein the source processor is configured to;

send a wake-up command to the sink processor via the auxiliary link;

negotiate one or more component capabilities of the sink processor via an interface that includes the primary link and the secondary link;

exchange one or more parameters with the sink processor dependent upon the one or more component capabilities;

send a plurality of initialization parameters to the sink processor via the primary link; and

send a synchronization signal to the sink processor via the primary link;

send a sleep command to the sink processor via the primary link responsive to the sending of the synchronization signal;

wherein the plurality of initialization parameters include a clock data recovery lock parameter, and an idle parameter.

2. The apparatus of claim 1, wherein the wake-up command includes a preamble, a wake with frequency change command, and a stop indicator.

3. The apparatus of claim 1, wherein the sink processor is configured to synchronize an internal timing circuit to an external timing reference responsive to the synchronization signal.

4. The apparatus of claim 1, wherein the clock data recovery lock parameter includes a number of clock recovery symbols needed for lock.

5. The apparatus of claim 1, further comprising a display coupled to the second processor.

6. A method, comprising:

signaling a first end of operation from a first component to a second component on a primary link between the first component and the second component;

deactivating, in response to the signaling of the first end of operation, the primary link;

signaling a start of operation from the first component to the second component, wherein the signaling includes transmitting a command on a secondary link, and a plurality of parameters on the primary link;

negotiating, via an interface that includes the primary link and the secondary link, one or more component capabilities between the first component and the second component in response to signaling the start of operation;

exchanging one or more parameters between the first component and the second component dependent upon the one or more component capabilities;

activating the primary link responsive to the signaling of the start of operation and dependent upon the plurality of parameters;

sending, responsive to the activation of the primary link, a synchronization signal from the first component to the second component;

signaling, responsive to the sending of the synchronization signal, a second end of operation from the first component to the second component on the primary link; and

deactivating, in the response to the signaling of the second end of operation, the primary link;

wherein the plurality of parameters include a clock recovery lock parameter and an idle parameter.

7. The method of claim 6, wherein the command on the secondary link includes a preamble, a wake with frequency change command, and a stop indicator.

8. The method of claim 6, further comprising, acknowledging, by the second component, the transmitted command on the secondary link.

9. The method of claim 6, wherein the synchronization signal is a vertical synchronization signal.

10. The method of claim 6, wherein the clock data recovery lock parameter includes a number of clock recovery symbols needed for lock.

11. A system, comprising:

a memory;

a first processor coupled to the memory;

a second processor coupled to the first processor through an interface; and

a display coupled to the second processor;

wherein the first processor is configured to;

negotiate with the second processor one or more component capabilities of the second processor via the interface;

exchange one or more parameters with the second processor dependent upon the one or more component capabilities;

transmit a signal to the second processor to activate a low power mode of the interface;

transmit a signal to the second processor to deactivate the low power mode of the interface;

transmit a synchronization signal to the second processor responsive to the deactivation of the low power mode of the interface;

transmit a signal to the second processor to re-activate the lower mode of the interface responsive to the transmission of the synchronization signal.

12. The system of claim 11, wherein the interface comprises a primary link and an auxiliary link.

13. The system of claim 12, wherein transmit a signal to the second processor to deactivate the low power mode of the interface includes transmitting a command on the auxiliary link.

14. The system of claim 13, wherein to transmit the signal to the second processor to deactivate the low power mode of the interface further includes transmitting a plurality of initialization parameters on the primary link.

15. The system of claim 11, wherein the synchronization signal is a vertical synchronization signal.

16. A method, comprising:

negotiating between a first processor and a second processor one or more component capabilities via an interface between the first processor to the second processor;

exchanging one or more parameters with the second processor dependent upon the one or more component capabilities;

activating a low power mode of the interface between the first processor and the second processor;

signaling, from the first processor to the second processor, an end to the low power mode;

deactivating the low power mode responsive to the signaling; and

sending, responsive to the deactivation of the low power mode, a synchronization signal from the first processor to the second processor;

re-activating the low power mode responsive to the sending of the synchronization signal.

17. The method of claim 16, wherein activating the low power mode of the interface comprises deactivating a primary link.

18. The method of claim 16, wherein signaling the end to the low power mode comprises sending a wake-up command through an auxiliary link from the first processor to the second processor.

19. The method of claim 16, wherein the synchronization signal is a vertical synchronization signal.

20. The method of claim 16, wherein deactivating the low power mode comprises sending a plurality of initialization parameters through the primary link from the first processor to the second processor.

21. A non-transitory computer accessible storage medium having program instructions stored therein that, in response to execution by a computer system, causes the computer system to perform operations including:

signaling a first end of operation from a first processor to a second processor on a primary link between the first processor and the second processor;

deactivating, in response to the signaling of the first end of operation, the primary link;

signaling a start of operation from the first processor to the second processor, wherein the signaling includes transmitting a command on a secondary link, a plurality of parameters on the primary link;

negotiating one or more component capabilities between the first component and the second component in response to signaling the start of operation via an interface that includes the primary link and the secondary link;

exchanging one or more parameters between the first component and the second component dependent upon the one or more component capabilities;

activating the primary link responsive to the signaling of the start of operation and dependent upon the plurality of parameters;

sending, responsive to the activation of the primary link, a synchronization signal from the first processor to the second processor;

signaling, responsive to the sending of the synchronization signal, a second end of operation from the first processor to the second processor on the primary link; and

deactivating, in the response to the signaling of the second end of operation, the primary link;

wherein the plurality of parameters include a clock recovery lock parameter and an idle parameter.

22. The non-transitory computer accessible storage medium of claim 21, wherein the command includes a preamble, a wake with frequency change command, and a stop indicator.

23. The non-transitory computer accessible storage medium of claim 21, wherein the idle parameter includes a number of lines before active operation begins.

24. The non-transitory computer accessible storage medium of claim 21, wherein the synchronization signal is a vertical synchronization signal.

25. The non-transitory computer accessible storage medium of claim 21, the clock data recovery lock parameter includes a number of clock recovery symbols needed for lock.