Intelligent dual data rate (DDR) memory controller
First Claim
1. A memory system, comprising:
- a first memory;
a first memory controller coupled to the first memory; and
a master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between the first memory and a second memory, under control of a second memory controller, using a system bus once;
wherein the first memory controller including the master controller module is configured to perform operations comprising;
receiving a source address and a destination address;
determining whether the source address is in the first memory;
determining whether the destination address is in the first memory; and
copying the destination address and data stored at the source address to the second memory controller using the system bus once in response to determining that the source address is in the first memory and the destination address is not in the first memory.
1 Assignment
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Accused Products
Abstract
Various embodiments include systems, methods, and devices configured to reduce the amount of information communicated via system buses/fabrics when transferring data to and from one or more memories. A system master component may send a source address and a destination address to a direct memory access controller inside of, or adjacent to, a memory controller. The direct memory access controller and/or the memory controller may determine whether the source and destination addresses are inside relevant portions of the memory. When both the source and destination are inside the relevant portion of the memory, the memory controller may perform a memory-to-memory data transfer without accessing the system bus.
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Citations
24 Claims
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1. A memory system, comprising:
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a first memory; a first memory controller coupled to the first memory; and a master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between the first memory and a second memory, under control of a second memory controller, using a system bus once; wherein the first memory controller including the master controller module is configured to perform operations comprising; receiving a source address and a destination address; determining whether the source address is in the first memory; determining whether the destination address is in the first memory; and copying the destination address and data stored at the source address to the second memory controller using the system bus once in response to determining that the source address is in the first memory and the destination address is not in the first memory. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A computing device, comprising:
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a system data bus; a processor coupled to the system data bus; and a memory system coupled to the system data bus, the memory system comprising; a first memory; a first memory controller coupled to the first memory; and a master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between the first memory and a second memory, under the control of a second memory controller, using the system bus once; wherein the first memory controller including the master controller module is configured to perform operations comprising; receiving a source address and a destination address; determining whether the source address is in the first memory; determining whether the destination address is in the first memory; and copying the destination address and data stored at the source address to the second memory controller using the system bus once in response to determining that the source address is in the first memory and the destination address is not in the first memory. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A method of transferring data to and from one or more memories, comprising:
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receiving a source address and a destination address in a first memory controller that includes a master controller module, the master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between a first memory under control of the first memory controller and a second memory, under control of a second memory controller, using a system bus once; determining in the first memory controller whether the source address is in the first memory; determining in the first memory controller whether the destination address is in the first memory; and copying the destination address and data stored at the source address to the second memory controller using the system bus once when the first memory controller determines that the source address is in the first memory and the destination address is not in the first memory. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A computing device, comprising:
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means for receiving a source address and a destination address in a first memory controller that includes a master controller module, the master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between a first memory under control of the first memory controller and a second memory, under control of a second memory controller, using a system bus once; means for determining in the first memory controller whether the source address is in the first memory; means for determining in the first memory controller whether the destination address is in the first memory; and means for copying the destination address and data stored at the source address to the second memory controller using the system bus once when the first memory controller determines that the source address is in the first memory and the destination address is not in the first memory. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification