Intelligent dual data rate (DDR) memory controller

• US 9,116,856 B2
• Filed: 11/08/2012
• Issued: 08/25/2015
• Est. Priority Date: 11/08/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Govindaraman, Ravikumar
• Primary Examiner(s): Tseng, Cheng-Yuan
• Assistant Examiner(s): Ahmed, Zubair
• Application Number:
  US13/672,346
• Publication Number:
  US 20140129766A1
• Time in Patent Office: 1,020 Days
• Field of Search: 711/105
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Various embodiments include systems, methods, and devices configured to reduce the amount of information communicated via system buses/fabrics when transferring data to and from one or more memories. A system master component may send a source address and a destination address to a direct memory access controller inside of, or adjacent to, a memory controller. The direct memory access controller and/or the memory controller may determine whether the source and destination addresses are inside relevant portions of the memory. When both the source and destination are inside the relevant portion of the memory, the memory controller may perform a memory-to-memory data transfer without accessing the system bus.

Claims

1. A memory system, comprising:

a first memory;

a first memory controller coupled to the first memory; and

a master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between the first memory and a second memory, under control of a second memory controller, using a system bus once;

wherein the first memory controller including the master controller module is configured to perform operations comprising;

receiving a source address and a destination address;

determining whether the source address is in the first memory;

determining whether the destination address is in the first memory; and

copying the destination address and data stored at the source address to the second memory controller using the system bus once in response to determining that the source address is in the first memory and the destination address is not in the first memory.

2. The memory system of claim 1, wherein the first memory controller is a double data rate (DDR) memory controller and the first memory is a DDR synchronous dynamic random-access memory.

3. The memory system of claim 1, wherein the first memory controller is a dynamic random-access memory (DRAM) memory controller.

4. The memory system of claim 1, wherein the second memory controller is a double data rate (DDR) memory controller and the second memory is a DDR synchronous dynamic random-access memory.

5. The memory system of claim 1, wherein the first memory controller including the master controller module is configured to perform operations further comprising:

pushing data stored at the source address onto the system bus in response to determining that the source address is in the first memory and the destination address is not in the first memory.

6. The memory system of claim 1, wherein the first memory controller including the master controller module is configured to perform operations further comprising:

pushing the destination address onto the system bus in response to determining that the source address is in the first memory and the destination address is not in the first memory.

7. A computing device, comprising:

a system data bus;

a processor coupled to the system data bus; and

a memory system coupled to the system data bus, the memory system comprising;

a first memory;

a first memory controller coupled to the first memory; and

a master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between the first memory and a second memory, under the control of a second memory controller, using the system bus once;

wherein the first memory controller including the master controller module is configured to perform operations comprising;

receiving a source address and a destination address;

determining whether the source address is in the first memory;

determining whether the destination address is in the first memory; and

copying the destination address and data stored at the source address to the second memory controller using the system bus once in response to determining that the source address is in the first memory and the destination address is not in the first memory.

8. The computing device of claim 7, wherein the first memory controller is a double data rate (DDR) memory controller and the first memory is a DDR synchronous dynamic random-access memory.

9. The computing device of claim 7, wherein the first memory controller is a dynamic random-access memory (DRAM) memory controller.

10. The computing device of claim 7, wherein the second memory controller is a double data rate (DDR) memory controller and the second memory is a DDR synchronous dynamic random-access memory.

11. The computing device of claim 7, wherein the first memory controller including the master controller module is configured to perform operations further comprising:

pushing data stored at the source address onto the system bus in response to determining that the source address is in the first memory and the destination address is not in the first memory.

12. The computing device of claim 7, wherein the first memory controller including the master controller module is configured to perform operations further comprising:

pushing the destination address onto the system bus in response to determining that the source address is in the first memory and the destination address is not in the first memory.

13. A method of transferring data to and from one or more memories, comprising:

receiving a source address and a destination address in a first memory controller that includes a master controller module, the master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between a first memory under control of the first memory controller and a second memory, under control of a second memory controller, using a system bus once;

determining in the first memory controller whether the source address is in the first memory;

determining in the first memory controller whether the destination address is in the first memory; and

copying the destination address and data stored at the source address to the second memory controller using the system bus once when the first memory controller determines that the source address is in the first memory and the destination address is not in the first memory.

14. The method of claim 13, further comprising:

pushing data stored at the source address onto the system bus in response to determining that the source address is in the first memory and the destination address is not in the first memory.

15. The method of claim 13, further comprising:

pushing the destination address onto the system bus in response to determining that the source address is in the first memory and the destination address is not in the first memory.

16. The method of claim 13, wherein receiving the source address and the destination address in the first memory controller comprises receiving the source address and the destination address from a peripheral component, or from a processing unit, through the system bus.

17. The method of claim 13, wherein determining in the first memory controller whether the source address is in the first memory comprises determining in a dynamic random-access memory (DRAM) memory controller whether the source address is in the first memory.

18. The method of claim 13, wherein determining in the first memory controller whether the source address is in the first memory comprises determining in a double data rate (DDR) memory controller whether the source address is in a DDR synchronous dynamic random-access memory.

19. A computing device, comprising:

means for receiving a source address and a destination address in a first memory controller that includes a master controller module, the master controller module included in the first memory controller configured to perform at least one direct memory access operation to effect at least one memory-to-memory data transfer operation between a first memory under control of the first memory controller and a second memory, under control of a second memory controller, using a system bus once;

means for determining in the first memory controller whether the source address is in the first memory;

means for determining in the first memory controller whether the destination address is in the first memory; and

means for copying the destination address and data stored at the source address to the second memory controller using the system bus once when the first memory controller determines that the source address is in the first memory and the destination address is not in the first memory.

20. The computing device of claim 19, further comprising:

means for pushing data stored at the source address onto the system bus in response to determining that the source address is in the first memory and the destination address is not in the first memory.

21. The computing device of claim 19, further comprising:

means for pushing the destination address onto the system bus in response to determining that the source address is in the first memory and the destination address is not in the first memory.

22. The computing device of claim 19, wherein the means for receiving the source address and the destination address in the first memory controller comprises means for receiving the source address and the destination address from a peripheral component or a processing unit through the system bus.

23. The computing device of claim 19, wherein the means for determining in the first memory controller whether the source address is in the first memory comprises means for determining in a dynamic random-access memory (DRAM) memory controller whether the source address is in the first memory.

24. The computing device of claim 19, wherein the means for determining in the first memory controller whether the source address is in the first memory comprises means for determining in a double data rate (DDR) memory controller whether the source address is in a DDR synchronous dynamic random-access memory.