Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns

• US 9,117,052 B1
• Filed: 06/28/2013
• Issued: 08/25/2015
• Est. Priority Date: 04/12/2012
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey, Cao, Min, Ruehl, Roland, Markham, Jeffrey
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US13/931,568
• Time in Patent Office: 788 Days
• Field of Search: 716/110, 716118-119, 716/139, 716/126, 716/131
• US Class Current: 1/1
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.

Claims

1. A computer implemented method for interactively implementing physical electronic designs with track patterns, comprising:

using a computing system having at least one processor or at least one processor core to execute a process, the process comprising;

identifying an area in an electronic design;

interactively defining, with an aid of an interactive design editing mechanism including or coupled with the at least one processor, a sub-area in the area and snapping at least one boundary segment related to the sub-area to one or more strip lines; and

assigning one or more track patterns to at least a region in the sub-area, wherein at least one track pattern includes a permitted legal arrangement of a plurality of routing tracks that are used to guide an electronic design automation tool.

2. The computer implemented method of claim 1, the process further comprising:

tessellating at least the area into multiple strips in a first direction with multiple strip lines, each of which divides two adjacent strips.

3. The computer implemented method of claim 1, the process further comprising:

displaying the one or more track pattern using one or more distinguishing representation schemes in a user interface.

4. The computer implemented method of claim 1, the process further comprising:

analyzing one or more adjacent layers that are adjacent to a layer on which the sub-area resides; and

identifying one or more characteristics of the one or more adjacent layers based at least in part upon a result of the act of analyzing the one or more adjacent layer.

5. The computer implemented method of claim 1, wherein the at least one boundary segment is a part of boundaries of circuit component design that comprise a bounding box of a component to be implemented in the sub-area and a halo extending beyond the bounding box.

6. The computer implemented method of claim 1, the process further comprising:

performing one or more sub-processes of multiple sub-processes, wherein;

a first sub-process of the multiple sub-process comprises;

reducing a number of track patterns to a reduced number of track patterns; and

assigning the reduced number of track patterns to the region for physical implementation of a component in the region;

a second sub-process of the multiple sub-process comprises;

determining whether there is an existing track pattern assigned to the region;

identifying or determining a constraint for track pattern from the component; and

determining whether the existing track pattern is to be used for physical implementation of the component in the region based at least in part upon the constraint identified or determined from the component;

a third sub-process of the multiple sub-process comprises;

determining the reduced number of track patterns based at least in part upon one or more first characteristics of the component or one or more second characteristics of an adjacent layer;

a fourth sub-process of the multiple sub-process comprises;

identifying or determining one or more guide layers for physical implementation of the component in the region;

a fifth sub-process of the multiple sub-process comprises;

identifying or determining one or more guide points for the component; and

snapping the one or more guide points to the one or more active tracks to implement the component in the region; and

a sixth sub-process of the multiple sub-process comprises;

determining whether there is a violation in physical implementation of the component in the region.

7. The computer implemented method of claim 1, the process further comprising:

tessellating a strip in a second direction to generate multiple regions, wherein

the multiple regions include the sub-area,

the act of snapping the at least one boundary segment related to the sub-area to one or more strip lines comprises automatically snapping the at least one boundary segment of boundaries to a strip line of the multiple strip lines, and

an enclosed area defined by the boundaries after the act of automatically snapping the at least one boundary segment is larger than an original area enclosed by the boundaries before the act of automatically snapping the at least one boundary segment.

8. The computer implemented method of claim 1, the process further comprising:

determining whether there is an existing feature in the sub-area; and

analyzing the existing feature in the sub-area to identify or determine one or more characteristics related to the existing feature, wherein

the one or more characteristics comprises one or more of one or more track patterns, one or more attributes of the one or more track patterns, a routing requirement or rule, a design rule, and geometric information about the existing feature.

9. The computer implemented method of claim 1, the process further comprising:

dynamically morphing the sub-area or boundaries of a circuit component design based at least in part upon one or more analyses of one or more adjacent layers of a layer on which the sub-area resides.

10. The computer implemented method of claim 1, the process further comprising:

identifying one or more valid track patterns, each of which encompasses at least boundaries based at least in part upon one or more characteristics of one or more adjacent layers or one or more sub-areas in proximity of the sub-area.

11. The computer implemented method of claim 1, the act of snapping the at least one boundary segment to the one or more strip lines further comprising:

identifying a first direction for implementing the electronic design in the sub-area;

identifying one or more first boundary segments in the first direction from boundaries of a circuit component design;

identifying one or more first strip lines in the first direction from the one or more strip lines; and

aligning the one or more first boundary segments to the one or more first strip lines.

12. The computer implemented method of claim 1, the act of snapping the at least one boundary segment to the one or more strip lines further comprising:

identifying a second direction for implementing the electronic design in the sub-area;

identifying one or more second boundary segments in the second direction from boundaries;

identifying one or more second strip lines in the second direction from the one or more strip lines; and

aligning the one or more second boundary segments to the one or more second strip lines.

13. The computer implemented method of claim 1, the process further comprising:

identifying a non-uniform track pattern that comprises multiple sets of tracks that correspond to more than one spacing value;

adding the non-uniform track pattern to the one or more track patterns; and

dynamically or interactively modifying the one or more track patterns based at least in part upon one or more characteristics of a circuit component design in the electronic design.

14. The computer implemented method of claim 1, the process further comprising:

determining boundaries related to the sub-area based at least in part upon a bounding box and a halo for a circuit component design, wherein the halo includes a non-uniform extension of a boundary of the circuit component design.

15. The computer implemented method of claim 1, the process further comprising:

identifying multiple hierarchical layers of a component design;

identifying relative locations among the multiple hierarchical layers;

identifying a set of available track patterns for a hierarchical layer of the multiple hierarchical layers;

determining a reduced set of available track patterns and one or more guide points for the hierarchical layer; and

implementing the component design across the multiple hierarchical layers by snapping the one or more guide points for the hierarchical layer to one or more tracks in the reduced set of available track patterns.

16. A system for interactively implementing physical electronic designs with track patterns, comprising:

at least one computing system having at least one processor or at least one processor core that executes one or more threads of execution;

a non-transitory computer accessible storage medium holding program code that includes a sequence of instructions that, when executed by the at least one processor or processor core, causes the at least one processor or processor core to at least identify an area in an electronic design, define a sub-area in the area, snap one or more boundary segments related to the sub-area to one or more strip lines, and assign one or more track patterns to at least a region of the multiple regions defined by the one or more strip lines in the sub-area, wherein at least one track pattern includes a plurality of routing tracks that are used to guide an electronic design automation tool.

17. The system of claim 16, in which the at least one computing system is further to:

execute one or more sets of instructions of multiple sets of instructions, wherein;

a first set of instructions of the multiple sets of instructions, when executed by the at least one computing system, causes the at least one computing system to snap at least one boundary segments related to the sub-area to one or more strip lines and to tessellate at least the area into multiple strips in a first direction with multiple strip lines, each of which divides two adjacent strips;

a second set of instructions of the multiple sets of instructions, when executed by the at least one computing system, causes the at least one computing system to tessellate a strip in a second direction to generate multiple regions, wherein the multiple regions include the sub-area;

a third set of instructions of the multiple sets of instructions, when executed by the at least one computing system, causes the at least one computing system to;

determine whether there is an existing feature in the sub-area; and

analyze the existing feature in the sub-area to identify or determine one or more characteristics related to the existing feature; and

a fourth set of instructions of the multiple sets of instructions, when executed by the at least one computing system, causes the at least one computing system to;

analyze one or more adjacent layers that are adjacent to a layer on which the sub-area resides; and

identify one or more characteristics of the one or more adjacent layers based at least in part upon a result of the act of analyzing the one or more adjacent layers.

18. The system of claim 17, in which the at least one computing system that is to snap the boundaries related to the sub-area to one or more strip lines is further to:

automatically snap a boundary segment of the boundaries to a strip line of the multiple strip lines.

19. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for interactively implementing physical electronic designs with track patterns, the method comprising:

using a computing system having at least one processor or at least one processor core to perform a process, the process comprising;

identifying an area in an electronic design;

defining a sub-area in the area;

snapping one or more boundary segments related to the sub-area to one or more strip lines; and

assigning one or more track patterns to at least a region of the multiple regions defined by the one or more strip lines in the sub-area, wherein at least one track pattern includes a plurality of routing tracks that are used to guide an electronic design automation tool.

20. The article of manufacture of claim 19, the process further comprising:

performing one or more sub-processes of multiple sub-processes, wherein;

a first sub-process of the multiple sub-processes comprises;

snapping at least one boundary segments related to the sub-area to one or more strip lines; and

tessellating at least the area into multiple strips in a first direction with multiple strip lines, each of which divides two adjacent strips;

a second sub-process of the multiple sub-processes comprises;

tessellating a strip in a second direction to generate multiple regions, wherein the multiple regions include the sub-area;

a third sub-process of the multiple sub-processes comprises;

determining whether there is an existing feature in the sub-area; and

analyzing the existing feature in the sub-area to identify or determine one or more characteristics related to the existing feature; and

a fourth sub-process of the multiple sub-processes comprises;

analyzing one or more adjacent layers that are adjacent to a layer on which the sub-area resides; and

identifying one or more characteristics of the one or more adjacent layers based at least in part upon a result of the act of analyzing the one or more adjacent layers.

21. The article of manufacture of claim 20, wherein the act of snapping the at least one boundary segment related to the sub-area to the one or more strip lines comprises:

automatically snapping a first boundary segment of the boundaries to a first strip line of the one or more strip lines.

22. The article of manufacture of claim 19, the method further comprising:

performing one or more sub-processes of multiple sub-processes, wherein

a first sub-process of the multiple sub-processes comprises;

reducing a number of track patterns to a reduced number of track patterns; and

assigning the reduced number of track patterns to the region for physical implementation of a component in the region;

a first sub-process of the multiple sub-processes comprises;

determining whether there is an existing track pattern assigned to the region;

identifying or determining a constraint for track pattern from the component; and

determining whether the existing track pattern is to be used for physical implementation of the component in the region based at least in part upon the constraint identified or determined from the component;

a second sub-process of the multiple sub-processes comprises;

determining the reduced number of track patterns based at least in part upon one or more first characteristics of the component or one or more second characteristics of an adjacent layer;

a third sub-process of the multiple sub-processes comprises;

determining whether there is a violation in physical implementation of the component in the region; and

a fourth sub-process of the multiple sub-processes comprises;

determining whether using a current layer including the region and an adjacent layer for the physical implementation resolves the violation;

identifying a characteristic of the adjacent layer; and

performing physical implementation of the component by using the current layer and the adjacent layer.