Image processing device, image processing system and bank management method

• US 9,117,298 B2
• Filed: 03/01/2012
• Issued: 08/25/2015
• Est. Priority Date: 03/29/2011
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tsuruta, Toru, Kaneko, Soutaro
• Primary Examiner(s): Faulk, Devona
• Assistant Examiner(s): Sun, Hai Tao
• Application Number:
  US13/409,696
• Publication Number:
  US 20120249834A1
• Time in Patent Office: 1,272 Days
• Field of Search: 345/565
• US Class Current: 1/1
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 5/005 Adapting incoming signals to the display format of the display terminal
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

An image processing device includes: first to third address registers that store three addresses, respectively, the three addresses indicating three bank regions, respectively; an input image bank managing unit that, when the image processing device receives an image from an imaging device, switches, between the first address register and the second address register, and sets a flag and supplies the address stored in the first address register as an address for writing the received image; an imaging processing unit that performs image processing on the received image; and an image processing bank managing unit that, when the flag is in a set state and the processed image is switched to another image to be processed, switches, between the second address register and the third address register, resets the flag and supplies to the image processing unit the address stored in the third address register.

Claims

1. An image processing device comprising:

a memory; and

a processor coupled to the memory and configured to;

set a first address of a first memory bank into an input bank register the input bank register designating the first memory bank to store a new image received from a camera,

set a second address of a second memory bank into a next process bank register, the next processed bank register designating the second memory bank to store a next image to be processed for display,

set a third address of a third memory bank into a processed bank register, the processed bank register designating the third memory bank to store an image to be currently processed for display,

store the new image received from the camera, into the first memory bank based on the first address,

first switch the first address and the second address, between the input bank register and the next processed bank register when the new image is stored into the first memory bank independently of a status of a flag,

set the flag when the first switch is completed;

process the image in the third memory bank for display,

second switch the first address and the third address, between the next processed bank register and the processed bank register, when the flag is set and the image in the third memory bank is processed for display,

reset the flag when the second switch is completed, and

wherein the first switch is executed independently of the status of the flag, and the second switch is executed according to the status of the flag.

2. The image processing device according to claim 1,

wherein, after the flag is reset and before the flag is set again, the processor does not switch between the next processed bank register and the processed bank register.

3. The image processing device according to claim 1,

wherein the processor is configured to;

receive a plurality of images from a plurality of cameras including the camera, and

store the plurality of images into a plurality of first memory banks including the first memory bank, respectively.

4. The image processing device according to claim 3,

wherein the processor is configured to set a plurality of flags including the flag respectively, based on a timing of storing of each of the plurality of images.

5. An image processing system comprising:

an imaging device including a camera which acquires a plurality of images;

a display device; and

an image processing device, including

a memory; and

a processor coupled to the memory and configured to;

set a first address of a first memory bank into an input bank register, the input bank register designating the first memory bank to store a new image received from the camera,

set a second address of a second memory bank into a next processed bank register, the next processed bank register designating the second memory bank to store a next image to be processed for display,

set a third address of a third memory bank into a processed bank register, the processed bank register designating the third memory bank to store an image to be currently processed for display,

store the new image received from the camera, into the first memory bank based on the first address,

first switch the first address and the second address, between the input bank register and the next processed bank register and when the new image is stored into the first memory bank independently of a status of a flag,

set the flag when the first switch is completed;

process the image in the third memory bank for display,

second switch the first address and the third address, between the next processed bank register and the processed bank register, when the flag is set and the image in the third memory bank is processed for display, and

reset the flag when the second switch is completed,

wherein the first switch is executed independently of the status of the flag, and the second switch is executed according to the status of the flag.

6. The image processing system according to claim 5,

wherein after the flag is reset and before the flag is set again, the processor does not switch between the next processed bank register and the processed bank register.

7. The image processing system according to claim 5,

wherein the processor is configured to:

receive a plurality of images from a plurality of cameras including the camera, and

store the plurality of images into a plurality of first memory banks including the first memory bank, respectively.

8. The image processing system according to claim 5,

wherein the processor is configured to set a plurality of flags including the flag respectively, based on a timing of storing of each of the plurality of images.

9. An image processing method executed by a computer, the image processing method comprising:

setting a first address of a first memory bank into an input bank register, the input bank register designating the first memory bank to store a new image received from a camera;

setting a second address of a second memory bank into a next processed bank register, the next processed bank register designating the second memory bank to store a next image to be processed by an image processing unit;

setting a third address of a third memory bank into a processed bank register, the processed bank register designating the third memory bank to store an image to be currently processed by the image processing unit;

storing the new image received from the camera, into the first memory bank based on the first address;

first switching the first address and the second address, between the input bank register and the next processed bank register when the storing of the new image is completed independently of a status of a flag;

setting the flag when the first switching is completed;

processing the image to be currently processed by the image processing unit;

second switching the first address and the third address, between the next processed bank register and the processed bank register, when the flag is set and the processing of the image by the image processing unit is completed; and

resetting the flag when the second switching is completed,

wherein the first switching is executed independently of the status of the flag, and the second switching is executed according to the status of the flag.

10. The image processing method according to claim 9,

wherein after the flag is reset and before the flag is set again there is no switching between the next processed bank register and the processed bank register.

11. The image processing method according to claim 9, wherein the processor is further configured to:

receive a plurality of images from a plurality of cameras including the camera; and

store the plurality of images into a plurality of first memory banks including the first memory bank, respectively.

12. The image processing method according to claim 9,

wherein the processor is configured to set a plurality of flags including the flag, respectively, based on a timing of storing each of the plurality of images.