Discrete three-dimensional memory comprising off-die address/data translator

• US 9,117,493 B2
• Filed: 03/06/2013
• Issued: 08/25/2015
• Est. Priority Date: 09/01/2011
• Status: Expired due to Fees

• Current Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Original Assignee: ChengDu HaiCun IP Technology LLC, Guobiao Zhang
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US13/787,796
• Publication Number:
  US 20130182483A1
• Time in Patent Office: 902 Days
• Field of Search: 257/296, 257/303, 257/311, 257/314, 257/315, 257/686, 438/238, 438/241, 438/257, 438/258, 438/262, 438/264, 438/266
• US Class Current: 1/1
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group

Abstract

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address-data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical space for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies.

Claims

1. A discrete three-dimensional memory (3D-M), comprising:

a first 3D-array die comprising at least a first 3D-M array including a plurality of vertically stacked memory cells;

a first peripheral-circuit die comprising an address/data translator for converting at least an address and/or data between logical space and physical space for said first 3D-array die;

a second peripheral-circuit die comprising a read/write-voltage generator for providing said first 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;

wherein said first 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.

2. The memory according to claim 1, further comprising a second 3D-array die comprising at least a second 3D-M array including a plurality of vertically stacked memory cells, wherein:

said address/data translator converts at least an address and/or data between logical space and physical space for said second 3D-array die;

said read/write-voltage generator provides said second 3D-array die with at least a read voltage and/or a write voltage other than the voltage supply;

said first 3D-array die, said second 3D-array die, said first peripheral-circuit die and said second peripheral-circuit die are separate dies.

3. The memory according to claim 1, wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

4. The memory according to claim 1, wherein said 3D-M comprises a three-dimensional mask-programmed read-only memory (3D-MPROM) or a three-dimensional electrically-programmable read-only memory (3D-EPROM).

5. The memory according to claim 1, wherein said 3D-M comprises at least one of a memristor, a resistive random-access memory (RRAM or ReRAM), a phase-change memory, a programmable metallization cell (PMC), and a conductive-bridging random-access memory (CBRAM).

6. The memory according to claim 1, wherein said address/data translator comprises at least one of an address mapping table, a faulty block table and a wear management table.

7. The memory according to claim 1, wherein said address/data translator comprises at least one of an ECC-encoder and an ECC-decoder.

8. The memory according to claim 1, wherein said 3D-array and peripheral-circuit dies are located in a memory package, a memory module, a memory card or a solid-state drive.

9. The memory according to claim 1, wherein said first peripheral-circuit die comprises fewer back-end layers than said first 3D-array die.

10. The memory according to claim 1, wherein said first peripheral-circuit die comprises different interconnect materials than said first 3D-array die.

11. The memory according to claim 1, wherein said first peripheral-circuit die comprises more substrate interconnect layers than said first 3D-array die.

12. The memory according to claim 1, wherein said second peripheral-circuit die comprises fewer back-end layers than said first 3D-array die.

13. The memory according to claim 1, wherein said second peripheral-circuit die comprises different interconnect materials than said first 3D-array die.

14. The memory according to claim 1, wherein said second peripheral-circuit die comprises more substrate interconnect layers than said first 3D-array die.

15. The memory according to claim 2, wherein said first peripheral-circuit die comprises fewer back-end layers than said second 3D-array die.

16. The memory according to claim 2, wherein said first peripheral-circuit die comprises different interconnect materials than said second 3D-array die.

17. The memory according to claim 2, wherein said first peripheral-circuit die comprises more substrate interconnect layers than said second 3D-array die.

18. The memory according to claim 2, wherein said second peripheral-circuit die comprises fewer back-end layers than said second 3D-array die.

19. The memory according to claim 2, wherein said second peripheral-circuit die comprises different interconnect materials than said second 3D-array die.

20. The memory according to claim 2, wherein said second peripheral-circuit die comprises more substrate interconnect layers than said second 3D-array die.