Pulse output circuit, shift register, and display device

• US 9,117,537 B2
• Filed: 05/19/2011
• Issued: 08/25/2015
• Est. Priority Date: 05/21/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Amano, Seiko, Miyake, Hiroyuki
• Primary Examiner(s): HOFFNER, LINH NGUYEN
• Application Number:
  US13/111,064
• Publication Number:
  US 20110285675A1
• Time in Patent Office: 1,559 Days
• Field of Search: 345/60, 345/87, 345/42, 345/204, 345/690, 345 76- 78, 345/90, 345 98-100, 345/559, 345/104, 345/211, 377/67, 377/64, 377/78, 377/79, 327/291
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06F 3/038 Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0871 with level shifting
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a bath mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch.

Claims

1. A pulse output circuit comprising:

a 1st transistor whose 1st electrode is electrically connected to a 1st input terminal, whose 2nd electrode is electrically connected to a 1st output terminal, and whose gate electrode is electrically connected to a 1st node;

a 2nd transistor whose 1st electrode is electrically connected to the 1st output terminal, whose 2nd electrode is electrically connected to a 1st power source line, and whose gate electrode is electrically connected to a 2nd node;

a 3rd transistor whose 1st electrode is electrically connected to the 1st input terminal, whose 2nd electrode is electrically connected to a 2nd output terminal, and whose gate electrode is electrically connected to the 1st node;

a 4th transistor whose 1st electrode is electrically connected to the 2nd output terminal, whose 2nd electrode is electrically connected to a 2nd power source line, and whose gate electrode is electrically connected to the 2nd node; and

a control portion configured to control levels of potentials supplied to the 1st node and the 2nd node,

wherein the 2nd power source line is provided so that a high-potential drive voltage and a low-potential drive voltage are switched and supplied.

2. The pulse output circuit according to claim 1, wherein the 1st to 4th transistors are n-channel transistors.

3. The pulse output circuit according to claim 1, further comprising a 5th transistor whose 1st electrode is electrically connected to the gate electrode of the 4th transistor, and whose 2nd electrode is electrically connected to the gate electrode of the 2nd transistor.

4. A display device comprising the pulse output circuit according to claim 1.

5. A pulse output circuit comprising:

1st to 11th transistors;

1st to 5th input terminals;

a 1st output terminal;

a 2nd output terminal; and

1st to 6th power source lines,

wherein a 1st electrode of the 1st transistor is electrically connected to the 1st input terminal, a 2nd electrode of the 1st transistor is electrically connected to a 1st electrode of the 2nd transistor and the 1st output terminal, and a gate electrode of the 1st transistor is electrically connected to a gate electrode of the 3rd transistor and a 1st electrode of the 7th transistor,

wherein a 2nd electrode of the 2nd transistor is electrically connected to the 1st power source line, and a gate electrode of the 2nd transistor is electrically connected to a gate electrode of the 4th transistor, a gate electrode of the 6th transistor, a 2nd electrode of the 9th transistor, a 2nd electrode of the 10th transistor, and a 1st electrode of the 11th transistor,

wherein a 1st electrode of the 3rd transistor is electrically connected to the 1st input terminal, and a 2nd electrode of the 3rd transistor is electrically connected to the 2nd output terminal,

wherein a 1st electrode of the 4th transistor is electrically connected to the 2nd output terminal, and a 2nd electrode of the 4th transistor is electrically connected to the 2nd power source line,

wherein a 1st electrode of the 5th transistor is electrically connected to a 2nd electrode of the 7th transistor, a 2nd electrode of the 5th transistor is electrically connected to the 3rd power source line, and a gate electrode of the 5th transistor is electrically connected to the 4th input terminal,

wherein a 1st electrode of the 6th transistor is electrically connected to a 1st electrode of the 5th transistor, and a 2nd electrode of the 6th transistor is electrically connected to the 1st power source line,

wherein a gate electrode of the 7th transistor is electrically connected to the 4th power source line,

wherein a 1st electrode of the 8th transistor is electrically connected to the 5th power source line, a 2nd electrode of the 8th transistor is electrically connected to a 1st electrode of the 9th transistor, and a gate electrode of the 8th transistor is electrically connected to the 2nd input terminal,

wherein a gate electrode of the 9th transistor is electrically connected to the 3rd input terminal,

wherein a 1st electrode of the 10th transistor is electrically connected to the 6th power source line, and a gate electrode of the 10th transistor is electrically connected to the 5th input terminal,

wherein a 2nd electrode of the 11th transistor is electrically connected to the 1st power source line, and a gate electrode of the 11th transistor is electrically connected to the 4th input terminal,

wherein the 1st power source line is provide so that a low-potential drive voltage is supplied,

wherein the 2nd power source line is provided so that a high-potential drive voltage and a low-potential drive voltage are switched and supplied and

wherein the 3rd to 6th power source lines are provided so that a high-potential drive voltage is supplied.

6. The pulse output circuit according to claim 5, wherein respective potentials of the 3rd power source line, the 4th power source line, the 5th power source line, and the 6th power source line are higher than respective potentials of the 1st power source line and the 2nd power source line.

7. The pulse output circuit according to claim 5, wherein the 1st to 11th transistors are n-channel transistors.

8. The pulse output circuit according to claim 5, further comprising a 12th transistor, wherein the 1st electrode of the 12th transistor is electrically connected to the gate electrode of the 4th transistor, and the 2nd electrode of the 12th transistor is electrically connected to the gate electrode of the 2nd transistor.

9. A display device comprising the pulse output circuit according to claim 5.

10. A shift register comprising:

at least a (m−

1)-th pulse output circuit, a m-th pulse output circuit, a (m+1)-th pulse output circuit, and a (m+2)-th pulse output circuit, where m is a natural number of greater than or equal to 2; and

1st to 4th signal lines provided so as to output clock signals,

wherein each of the (m−

1)-th pulse output circuit, the m-th pulse output circuit, the (m+1)-th pulse output circuit, and the (m+2)-th pulse output circuit comprises 1st to 5th input terminals and 1st and 2nd output terminals,

wherein the 1st to 3rd input terminals of the m-th pulse output circuit are electrically connected to three signal lines among the 1st to 4th signal lines,

wherein the 4th input terminal of the m-th pulse output circuit is electrically connected to the 1st output terminal of the (m−

1)-th pulse output circuit,

wherein the 5th input terminal of the m-th pulse output circuit is electrically connected to the 1st output terminal of the (m+2)-th pulse output circuit,

wherein the 1st output terminal of the m-th pulse output circuit is electrically connected to the 4th input terminal of the (m+1)-th pulse output circuit,

wherein the 1st to 4th signal lines output clock signals which are sequentially delayed by ¼

period, and

wherein each of the (m-1)-th pulse output circuit, the m-th pulse output circuit, the (m+1)-th pulse output circuit, and the (m+2)-th pulse output circuit comprises;

a 1st transistor whose 1st electrode is electrically connected to the 1st input terminal, whose 2nd electrode is electrically connected to the 1st output terminal, and whose gate electrode is electrically connected to a 1st node;

a 2nd transistor whose 1st electrode is electrically connected to the 1st output terminal, whose 2nd electrode is electrically connected to a 1st power source line, and whose gate electrode is electrically connected to a 2nd node;

a 3rd transistor whose 1st electrode is electrically connected to the 1st input terminal, whose 2nd electrode is electrically connected to the 2nd output terminal, and whose gate electrode is electrically connected to the 1st node;

a 4th transistor whose 1st electrode is electrically connected to the 2nd output terminal, whose 2nd electrode is electrically connected to a 2nd power source line, and whose gate electrode is electrically connected to the 2nd node; and

a control portion configured to control levels of potentials supplied to the 1st node and the 2nd node,

wherein the 2nd power source line is provided so that a high-potential drive voltage and a low-potential drive voltage are switched and supplied.

11. A display device comprising the shift register according to claim 10.