Reduced stress high voltage word line driver

• US 9,117,547 B2
• Filed: 05/06/2013
• Issued: 08/25/2015
• Est. Priority Date: 05/06/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: International Business Machines Corporation
• Inventors: Barth, John E. Jr.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US13/887,508
• Publication Number:
  US 20140328122A1
• Time in Patent Office: 841 Days
• Field of Search: 365/182, 365/230.06, 365/149, 365/189.11, 365/226, 327/108
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge

Abstract

Exemplary embodiments of the present invention disclose a method and system for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line with a word line driver logic that is composed of thin-oxide MOS transistors, wherein the thin-oxide MOS transistors experience less than the voltage difference on the word line between any two of a source, a drain, and a gate. In a step, charging the word line from the low voltage to an intermediate voltage level. In another step, charging the word line to the high voltage from the intermediate voltage level.

Claims

1. A word line driver logic adapted for connection to a corresponding word line in a memory logic, the word line driver logic comprising:

a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a control signal which varies as a function of an input signal supplied to the word line driver logic;

a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding word line, and a gate coupled to a second voltage supply providing a second voltage level;

a third transistor including a first source/drain coupled to the corresponding word line, a second source/drain, and a gate coupled to the second voltage level;

a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a third voltage supply providing a third voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal;

a fifth transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled the second voltage level, and a gate coupled to the gate of the first transistor; and

a sixth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled the second voltage level, and a gate coupled to the gate of the fourth transistor;

wherein the second voltage level is configured such that a voltage difference between the first and second source/drains of the first transistor and the fourth transistor is less than a voltage difference between the first and third voltage supplies.

2. The word line driver logic of claim 1, wherein each of the first, second, third, fourth, fifth and sixth transistors is a thin-oxide MOS transistor.

3. The word line driver logic of claim 1, wherein each of the first, second and sixth transistors is a thin-oxide PMOS transistor, and each of the third, fourth and fifth transistors is a thin-oxide NMOS transistor.

4. The word line driver logic of claim 1, wherein the first voltage level is higher than the second and third voltage levels, and wherein the second voltage level is higher than the third voltage level.

5. The word line driver logic of claim 1, further comprising at least one of:

a first voltage level shifter logic coupled to the gates of the first transistor and the fifth transistor, the first voltage level shifter logic being operative to receive the input signal referenced to a first set of signal levels and to generate the control signal referenced to a second set of signal levels; and

a second voltage level shifter logic coupled to the gates of the fourth transistor and the sixth transistor, the second voltage level shifter logic being operative to receive the input signal referenced to the first set of signal levels and to generate the second control signal referenced to a third set of signal levels.

6. The word line driver logic of claim 1, wherein the memory logic is a DRAM.

7. A method for asserting a voltage transition from a low voltage to a high voltage with a voltage difference between the low and high voltages on a word line in a memory logic with a word line driver logic that is composed of thin-oxide MOS transistors, wherein the thin-oxide MOS transistors experience less than the voltage difference on the word line between any two of a source, a drain, and a gate, the method comprising the steps of:

charging the word line from the low voltage to an intermediate voltage that is higher than the low voltage and lower than the high voltage when transitioning the word line from the low voltage to the high voltage; and

charging the word line to the high voltage from the intermediate voltage when transitioning the word line from the low voltage to the high voltage;

discharging the word line from the high voltage to the intermediate voltage when transitioning the word line from the high voltage to the low voltage; and

discharging the word line from the intermediate voltage to the low voltage when transitioning the word line from the low voltage to the high voltage.

8. The method of claim 7, wherein the thin-oxide transistors are three PMOS and three NMOS thin-oxide transistors.

9. The method of claim 7, wherein the memory logic is a DRAM.

10. The method of claim 7, wherein the low voltage is a negative voltage and the intermediate voltage is half way between the low voltage and the high voltage.

11. The method of claim 7, wherein the word driver logic is supplied with at least three voltage levels, the low voltage level, the intermediate voltage level, and the high voltage level.

12. The method of claim 7, wherein the word line logic includes a first voltage level shifter logic being operative to receive an input signal referenced to a first set of signal levels and to generate a control signal referenced to a second set of signal levels and a second voltage level shifter logic being operative to receive the input signal referenced to the first set of signal levels and to generate a second control signal referenced to a third set of signal levels.

13. The method of claim 12, wherein the first voltage level shifter responds quickly to a rising input and slowly to a falling input and the second voltage shifter responds quickly to a falling input and slowly to a rising input.

14. The method of claim 13, wherein there is a delay between the charging of the word line to the intermediate voltage step and the charging of the word line to the high voltage step and a delay between the discharging of the word line to the intermediate voltage step and the discharging of the word line to the low voltage step.

15. A 2X voltage driver logic adapted for 2X voltage output, 2X being a voltage that is twice a voltage limit of a thin oxide MOSFET device, the 2X voltage driver logic comprising:

a first transistor including a first source/drain coupled to a first voltage supply providing a first voltage level, a second source/drain, and a gate adapted to receive a control signal which varies as a function of an input signal supplied to the 2X voltage driver logic;

a second transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled to the corresponding 2X voltage output, and a gate coupled to a second voltage supply providing a second voltage level;

a third transistor including a first source/drain coupled to the corresponding 2X voltage output, a second source/drain, and a gate coupled to the second voltage level;

a fourth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled to a third voltage supply providing a third voltage level, and a gate adapted to receive a second control signal which varies as a function of the input signal;

a fifth transistor including a first source/drain connected to the second source/drain of the first transistor, a second source/drain coupled the second voltage level, and a gate coupled to the gate of the first transistor; and

a sixth transistor including a first source/drain connected to the second source/drain of the third transistor, a second source/drain coupled the second voltage level, and a gate coupled to the gate of the fourth transistor;

wherein the second voltage level is configured such that a voltage difference between the first and second source/drains of the first transistor and the fourth transistor is less than a voltage difference between the first and third voltage supplies.

16. The 2X voltage driver logic of claim 15, wherein each of the first, second, third, fourth, fifth and sixth transistors is a thin-oxide MOS transistor.

17. The 2X voltage driver logic of claim 15, wherein each of the first, second and sixth transistors is a thin-oxide PMOS transistor, and each of the third, fourth and fifth transistors is a thin-oxide NMOS transistor.

18. The 2X voltage driver logic of claim 15, wherein the first voltage level is higher than the second and third voltage levels, and wherein the second voltage level is higher than the third voltage level.

19. The 2X voltage driver logic of claim 15, further comprising at least one of:

a first voltage level shifter logic coupled to the gates of the first transistor and the fifth transistor, the first voltage level shifter logic being operative to receive the input signal referenced to a first set of signal levels and to generate the control signal referenced to a second set of signal levels; and

a second voltage level shifter logic coupled to the gates of the fourth transistor and the sixth transistor, the second voltage level shifter logic being operative to receive the input signal referenced to the first set of signal levels and to generate the second control signal referenced to a third set of signal levels.