Carbon layer and method of manufacture

• US 9,117,667 B2
• Filed: 07/11/2012
• Issued: 08/25/2015
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Dal, Markvan
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US13/546,188
• Publication Number:
  US 20140017883A1
• Time in Patent Office: 1,140 Days
• Field of Search: 257/E21.09, 257/E21.296, 438/664
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02378 Silicon carbide
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02491 Conductive materials
• CPC Class Codes: H01L 21/02527 Carbon, e.g. diamond-like carbon
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 29/1606 Graphene
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A system and method for manufacturing a carbon layer is provided. An embodiment comprises depositing a first metal layer on a substrate, the substrate comprising carbon. A silicide is epitaxially grown on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide. In an embodiment the carbon layer is graphene, and may be transferred to a semiconductor substrate for further processing to form a channel within the graphene.

Claims

1. A method for manufacturing a channel material, the method comprising:

depositing a first metal layer on a substrate, the substrate comprising silicon carbon, wherein the silicon carbon has a (111) crystalline orientation;

epitaxially growing a silicide on the substrate, the epitaxially growing the silicide also forming a layer of carbon over the silicide, wherein the layer of carbon is a product from a reaction of the first metal layer and the substrate; and

curing the layer of carbon with a first anneal, wherein the curing the layer of carbon is performed after the epitaxially growing the silicide on the substrate.

2. The method of claim 1, wherein the layer of carbon is graphene.

3. The method of claim 1, wherein the epitaxially growing the silicide further comprises performing a second anneal.

4. The method of claim 3, wherein the performing the second anneal is performed at least in part at a temperature of less than about 800°

C.

5. The method of claim 1, further comprising:

transferring the layer of carbon to a semiconductor substrate; and

forming a transistor from at least a portion of the layer of carbon.

14. The method of claim 1, wherein, prior to the depositing the first metal layer on the substrate, the silicide is chosen such that a lattice constant of the silicide is close to a lattice constant of the substrate.

15. The method of claim 3, wherein the performing the first anneal is performed at least in part at a temperature of less than about 200°

C.

18. The method of claim 1, wherein the silicon carbon has a thickness between about 0.5 μ

m and about 500 μ

m.

6. A method of manufacturing a semiconductor device, the method comprising:

forming a first metal layer over a carbon-containing substrate, wherein the carbon-containing substrate has a (111) crystalline orientation; and

annealing the first metal layer and the carbon-containing substrate to form a first silicide region and a graphene layer from the first metal layer and the carbon-containing substrate, wherein the graphene layer is located over the first silicide region, wherein the annealing the first metal layer and the carbon-containing substrate is performed at a temperature of less than 200°

C. and causes the first silicide region to be epitaxially grown.

7. The method of claim 6, wherein the first metal layer has a thickness of less than about 10 nm.

8. The method of claim 6, wherein the carbon-containing substrate comprises silicon carbon.

9. The method of claim 6, further comprising:

removing the graphene layer from the first silicide region using a transfer layer; and

placing the graphene layer onto a semiconductor substrate.

16. The method of claim 6, wherein the carbon-containing substrate comprises silicon germanium carbon.

19. The method of claim 6, further comprising an insulator located beneath the carbon-containing substrate.

10. A method of manufacturing a semiconductor device, the method comprising:

providing a substrate comprising carbon, the substrate having a first lattice constant and a (111) crystalline orientation;

depositing a first metal layer in contact with the substrate; and

forming a carbon layer over the substrate, wherein the carbon layer is graphene, the forming the carbon layer comprising growing a monocrystalline silicide on the substrate, the monocrystalline silicide having a second lattice constant the same as the first lattice constant, wherein the carbon layer comprises carbon from the substrate; and

curing the carbon layer after the forming the carbon layer, wherein the forming the carbon layer is performed at least in part using a first anneal and the curing the carbon layer is performed at least in part using a second anneal different from the first anneal, and wherein the second anneal occurs after the growing the monocrystalline silicide.

11. The method of claim 10, wherein the first anneal further comprises annealing the substrate and the first metal layer at a temperature less than about 800°

C.

12. The method of claim 10, further comprising:

separating the carbon layer from the monocrystalline silicide;

transferring the carbon layer to a semiconductor substrate; and

forming a channel within the carbon layer.

13. The method of claim 10, wherein the first metal layer has a thickness of less than about 10 nm.

17. The method of claim 11, wherein the forming the carbon layer further comprises annealing the substrate and the first metal layer at a temperature less than about 200°

C.

20. The method of claim 10, wherein the first metal layer comprises platinum, cobalt, palladium, copper, or iron.