Device architecture and method for precision enhancement of vertical semiconductor devices

• US 9,117,709 B2
• Filed: 11/26/2013
• Issued: 08/25/2015
• Est. Priority Date: 11/26/2012
• Status: Active Grant

• Current Assignee: D3 Semiconductor LLC (D3 Semiconductor Asia Sdn. Bhd.)
• Original Assignee: D3 Semiconductor LLC (D3 Semiconductor Asia Sdn. Bhd.)
• Inventors: Harrington, Thomas E. III
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US14/091,315
• Publication Number:
  US 20140145240A1
• Time in Patent Office: 637 Days
• Field of Search: 438/10, 257/139
• US Class Current: 1/1
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5258 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

Improvement of key electrical specifications of vertical semiconductor devices, usually found in the class of devices known as discrete semiconductors, has a direct impact on the performance achievement and power efficiency of the systems in which these devices are used. Imprecise vertical device specifications cause system builders to either screen incoming devices for their required specification targets or to design their system with lower performance or lower efficiency than desired. Disclosed is an architecture and method for achieving a desired target specification for a vertical semiconductor device. Precise trimming of threshold voltage improves targeting of both on-resistance and switching time. Precise trimming of gate resistance also improves targeting of switching time. Precise trimming of a device'"'"'s effective width improves targeting of both on-resistance and current-carrying capability. Device parametrics are trimmed to improve a single device, or a parametric specification is targeted to match specifications on two or more devices.

Claims

1. A method of making a vertical field effect device having a drain terminal, a source terminal and a gate terminal, the method comprising:

providing a first field effect device connected to the drain terminal, the source terminal and the gate terminal;

providing a set of second field effect devices, connected to the source terminal by a set of parallel activation fuses and connected to the gate terminal by a set of series isolation fuses;

measuring a device parameter measurement value;

comparing the device parameter measurement value to a target value; and

,

if the device parameter measurement value meets the target value, then blowing a parallel activation fuse of the set of parallel activation fuses.

2. The method of claim 1, wherein the step of blowing further comprises blowing a plurality of parallel activation fuses of the set of parallel activation fuses.

3. The method of claim 1, comprising the further step of:

if the device parameter measurement value does not meet the target value, then blowing a series isolation fuse of the set of series of isolation fuses.

4. The method of claim 1, wherein the step of measuring further comprises measuring a threshold voltage.

5. The method of claim 1, wherein the step of measuring further comprises measuring an on-resistance value.

6. The method of claim 1, wherein the step of providing the set of second field effect devices further comprises the step of:

providing a set of resistors connected to the set of parallel activation fuses.

7. The method of claim 1, wherein the gate terminal is further connected to a trimmable parallel resistor network and further comprising the step of:

blowing a parallel resistor fuse of the parallel resistor network.