Porting a circuit design from a first semiconductor process to a second semiconductor process

• US 9,117,746 B1
• Filed: 07/21/2014
• Issued: 08/25/2015
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Clark, Lawrence T., Thompson, Scott E., Roy, Richard S., Leshner, Samuel
• Primary Examiner(s): Memula, Suresh
• Application Number:
  US14/336,793
• Time in Patent Office: 400 Days
• Field of Search: 716/51, 716/52, 716/54
• US Class Current: 1/1
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Porting includes determining processing targets for the second semiconductor manufacturing process.

Claims

1. A method of fabricating an integrated circuit comprising:

producing a second transistor circuit design based on a first transistor circuit design, the second transistor circuit design having target transistors, the target transistors including a plurality of deeply depleted channel (DDC) transistors, the second design having an initial threshold voltage value assigned to each of the target transistors;

determining targets defining a set of design constraints;

solving objective functions with the set of design constraints to produce optimized threshold voltage values for each of the target transistors;

selectively doping a semiconductor substrate to form a plurality of highly-doped screening regions over which a corresponding plurality of transistor gates will respectively be formed;

selectively doping the semiconductor substrate in regions that are associated with the target transistors to dopant concentrations that set the threshold voltage values for each of the target transistors to a desired range of values; and

forming an undoped semiconductor layer above the highly doped screening region.

2. The method of claim 1, wherein the first transistor circuit design is a bit cell and the second transistor circuit design is a bit cell.

3. The method of claim 1, wherein the target transistors of the second transistor circuit design each have a gate length and a gate width;

and

further comprising;

determining targets for the gate length and gate width of the target transistors of the second transistor circuit design.

4. The method of claim 3, wherein the optimized the threshold voltage values for each of the target transistors comprises an optimized gate length or an optimized gate width for each of the DDC transistors.

5. The method of claim 4, wherein selectively doping the target transistors comprises using a mask pattern that is designed based upon the optimized gate length or the optimized gate width the of each of the DDC transistors.

6. The method of claim 2, wherein the bit cell is a six-transistor static random access memory (SRAM) cell.

7. The method of claim 1, wherein forming an undoped semiconductor layer comprises growing an epitaxial layer.

8. The method of claim 1, wherein at least one of the plurality of DDC transistors is an n-channel transistor.

9. The method of claim 1, wherein at least one of the plurality of DDC transistors is a p-channel transistor.

10. The method of claim 1, further comprising forming source/drain extension regions above the highly-doped screening region.

11. An integrated circuit structure comprising:

a plurality of target transistors configured in a second transistor circuit design based on a first transistor circuit design, the plurality of target transistors including a plurality of deeply depleted channel (DDC) transistors, the second transistor circuit design having an initial threshold voltage value assigned to each one of the plurality of target transistors;

wherein the each target transistor of the plurality of target transistors has a functional target defined by a set of design constraints, and the initial threshold voltage value is specified by a solution of objective functions within the design constraints;

a semiconductor substrate having a plurality of highly-doped screening regions each one under a corresponding one of a plurality of target transistor gates;

a portion of the plurality of highly-doped screening regions further comprising doped regions configured to set the threshold voltage value for each of the target transistors;

an undoped semiconductor layer formed above the highly doped screening region.

12. The structure of claim 11, wherein the first and the second transistor circuit designs are memory bit cells.

13. The structure of claim 12, wherein the first and the second transistor circuit designs are static random access memory (SRAM) cells.

14. The structure of claim 13, wherein the memory bit cell is a six-transistor SRAM cell.

15. The structure of claim 11, wherein the undoped semiconductor layer comprises an epitaxial layer.

16. The structure of claim 11, wherein at least one of the plurality of DDC transistors is an n-channel transistor.

17. The structure of claim 11, wherein at least one of the plurality of DDC transistors is a p-channel transistor.

18. The structure of claim 11, further comprising source/drain extension regions above the highly-doped screening region.