Semiconductor device and structure

• US 9,117,749 B1
• Filed: 03/15/2013
• Issued: 08/25/2015
• Est. Priority Date: 03/15/2013
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Au, Bac
• Assistant Examiner(s): Nguyen, Sophia
• Application Number:
  US13/836,080
• Time in Patent Office: 893 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1436 Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1438 Flash memory
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 : adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/883 : Oxides or nitrides
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A semiconductor device, including: a first transistor sharing a first diffusion with a second transistor; a third transistor sharing a second diffusion with the second transistor; and at least one programmable resistor; wherein the at least one programmable resistor is connected to the first diffusion and the second diffusion, wherein the at least one programmable resistor includes one of the following: memristor, transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure.

Claims

1. A semiconductor device, comprising:

a first transistor sharing a first diffusion with a second transistor;

a third transistor sharing a second diffusion with said second transistor; and

a fourth transistor sharing a third diffusion with a fifth transistor;

a sixth transistor sharing a fourth diffusion with said fifth transistor,

wherein said device comprises;

a first layer comprising a first number of said transistors overlaid by

a second layer comprising a second number of said transistors;

a first programmable resistor; and

a second programmable resistor;

wherein said first programmable resistor is connected to said first diffusion and said second diffusion, and

said second programmable resistor is connected to said third diffusion and said fourth diffusion,

wherein at least one of said first number of said transistors is self-aligned to at least one of said second number of said transistors, and

wherein a portion of said first programmable resistor is disposed either to a side isolation region of said second transistor or directly above a top isolation region of said second transistor, and

wherein said programmable resistors comprise one of the following;

memristor, transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure.

2. A semiconductor device according to claim 1,

wherein said first programmable resistor overlays said second transistor, and said second programmable resistor overlays said fifth transistor.

3. A semiconductor device according to claim 1,

wherein said fourth transistor overlays said first transistor.

4. A semiconductor device according to claim 1,

wherein said transistors are horizontally oriented transistors.

5. A semiconductor device according to claim 1,

wherein said transistors comprise mono-crystalline material.

6. A semiconductor device according to claim 1,

wherein said first programmable resistor is overlaying said second programmable resistor.

7. A semiconductor device according to claim 1, further comprising:

third programmable resistor,

wherein each of said programmable resistor is connected to the diffusions of their respective transistor.

8. A semiconductor device, comprising:

a first transistor sharing a first diffusion with a second transistor;

a third transistor sharing a second diffusion with said second transistor;

a fourth transistor sharing a third diffusion with a fifth transistor;

a sixth transistor sharing a fourth diffusion with said fifth transistor;

wherein said fourth transistor overlays said first transistor, and

said fifth transistor overlays said second transistor, and

said sixth transistor overlays said third transistor,

a first programmable resistor; and

a second programmable resistor;

wherein said first programmable resistor is connected to said first diffusion and said second diffusion, and

said second programmable resistor is connected to said third diffusion and said fourth diffusion,

wherein said fourth transistor is self-aligned to said first transistor, and

wherein a portion of said first programmable resistor is disposed either to a side isolation region of said second transistor or directly above a top isolation region of said second transistor.

9. A semiconductor device according to claim 8, wherein

said programmable resistors comprise one of the following:

memristor, transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure.

10. A semiconductor device according to claim 8,

wherein said fourth transistor overlays said first transistor.

11. A semiconductor device according to claim 8,

wherein said transistors are horizontally oriented transistors.

12. A semiconductor device according to claim 8,

wherein said transistors comprise mono-crystalline material.

13. A semiconductor device according to claim 8,

wherein said first programmable resistor overlays said second transistor, and said second programmable resistor overlays said fifth transistor.

14. A semiconductor device according to claim 8,

wherein said first transistor and said second transistor and said third transistor are in the same layer.

15. A 3D semiconductor device, comprising:

a first transistor sharing a first diffusion with a second transistor;

a third transistor sharing a second diffusion with said second transistor;

a fourth transistor sharing a third diffusion with a fifth transistor;

a sixth transistor sharing a fourth diffusion with said fifth transistor,

wherein said device comprises;

a first layer comprising a first number of said transistors overlaid by

a second layer comprising a second number of said transistors;

a first programmable resistor; and

a second programmable resistor;

wherein said first programmable resistor is connected to said first diffusion and said second diffusion, and

said second programmable resistor is connected to said third diffusion and said fourth diffusion, and

wherein said transistors comprise mono-crystalline material,

wherein at least one of said first number of said transistors is self-aligned to at least one of said second number of said transistors, and

wherein a portion of said first programmable resistor is disposed either to a side isolation region of said second transistor or directly above a top isolation region of said second transistor.

16. A 3D semiconductor device according to claim 15,

wherein said transistors are horizontally oriented transistors.

17. A 3D semiconductor device according to claim 15,

wherein said first programmable resistor overlays said second transistor, and said second programmable resistor overlays said fifth transistor.

18. A 3D semiconductor device according to claim 15, wherein said programmable resistors comprise one of the following:

memristor, transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure, and

wherein said transistors are horizontally oriented transistors.

19. A 3D semiconductor device according to claim 15,

wherein said fourth transistor overlays said first transistor.

20. A 3D semiconductor device according to claim 15,

wherein said first transistor and said second transistor and said third transistor are in the same layer.