Air-spacer MOS transistor
First Claim
Patent Images
1. A method for manufacturing a MOS transistor comprising:
- forming a gate stack having a height, a length, and a width and comprising a lower portion, a middle portion and an upper portion;
forming around the gate stack at least one first spacer surrounded with another material;
removing the first spacer to form a cavity on each side of the gate stack;
decreasing the length of the middle portion of the gate stack in said cavity such that the length of the middle portion is less than the lengths of the lower and upper portions;
closing an upper aperture of the cavity by a non-conformal method while depositing a dielectric layer on the walls of the gate stack with the decreased length middle portion so as to provide an air spacer;
removing the lower, decreased length middle and upper portions of the gate stack to provide a gate stack opening; and
filling the gate stack opening with a conductive metal to form a metal gate having a lower conductive portion, a middle conductive portion and an upper conductive portion, wherein the length of the middle conductive portion is less than the lengths of the lower and upper conductive portions.
2 Assignments
0 Petitions
Accused Products
Abstract
A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.
-
Citations
15 Claims
-
1. A method for manufacturing a MOS transistor comprising:
-
forming a gate stack having a height, a length, and a width and comprising a lower portion, a middle portion and an upper portion; forming around the gate stack at least one first spacer surrounded with another material; removing the first spacer to form a cavity on each side of the gate stack; decreasing the length of the middle portion of the gate stack in said cavity such that the length of the middle portion is less than the lengths of the lower and upper portions; closing an upper aperture of the cavity by a non-conformal method while depositing a dielectric layer on the walls of the gate stack with the decreased length middle portion so as to provide an air spacer; removing the lower, decreased length middle and upper portions of the gate stack to provide a gate stack opening; and filling the gate stack opening with a conductive metal to form a metal gate having a lower conductive portion, a middle conductive portion and an upper conductive portion, wherein the length of the middle conductive portion is less than the lengths of the lower and upper conductive portions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. A method for manufacturing a MOS transistor comprising:
-
forming a gate stack having a height, a length, and a width and comprising a lower portion, a middle portion and an upper portion; forming around the gate stack a first spacer surrounded with another material; removing the first spacer to form a cavity in said another material; reducing a length of the middle portion of the gate stack in said cavity relative to the lengths of the lower and upper portions; lining side walls of the cavity and the gate stack with an insulating material; closing an upper aperture of the cavity so as to provide an air spacer defined by the lined side walls; removing the gate stack to provide a gate stack opening; and filling the gate stack opening with a conductive metal to form a metal gate having a lower conductive portion, a middle conductive portion and an upper conductive portion, wherein the length of the middle conductive portion is less than the lengths of the lower and upper conductive portions. - View Dependent Claims (12, 13, 14, 15)
-
Specification