Air-spacer MOS transistor

• US 9,117,805 B2
• Filed: 01/31/2014
• Issued: 08/25/2015
• Est. Priority Date: 02/04/2013
• Status: Active Grant

• Current Assignee: Commissariat a L'Energie Atomique (AES Corporation), STMicroelectronics SA (STMicroelectronics NV), STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: Commissariat a L'Energie Atomique (AES Corporation), STMicroelectronics SA (STMicroelectronics NV), STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Niebojewski, Heimanu, Morand, Yves, Le Royer, Cyrille
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): DINKE, BITEW A
• Application Number:
  US14/169,913
• Publication Number:
  US 20140217520A1
• Time in Patent Office: 571 Days
• Field of Search: 438/421, 257/410
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4991 comprising an air gap
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location

Abstract

A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Claims

1. A method for manufacturing a MOS transistor comprising:

forming a gate stack having a height, a length, and a width and comprising a lower portion, a middle portion and an upper portion;

forming around the gate stack at least one first spacer surrounded with another material;

removing the first spacer to form a cavity on each side of the gate stack;

decreasing the length of the middle portion of the gate stack in said cavity such that the length of the middle portion is less than the lengths of the lower and upper portions;

closing an upper aperture of the cavity by a non-conformal method while depositing a dielectric layer on the walls of the gate stack with the decreased length middle portion so as to provide an air spacer;

removing the lower, decreased length middle and upper portions of the gate stack to provide a gate stack opening; and

filling the gate stack opening with a conductive metal to form a metal gate having a lower conductive portion, a middle conductive portion and an upper conductive portion, wherein the length of the middle conductive portion is less than the lengths of the lower and upper conductive portions.

2. The method of claim 1, wherein decreasing the length of the middle portion produces a length equal to from 0.3 to 0.9 the length of the lower and upper portions of the gate stack.

3. The method of claim 1, wherein the air spacer extends along said length of the gate stack and is provided on opposite sides of the gate stack.

4. The method of claim 3, wherein the dielectric layer on the walls of the gate stack delimits said air spacer.

5. The method of claim 1, wherein the lower portion of the gate stack comprises a first material and the middle portion of the gate stack comprises a second material.

6. The method of claim 5, wherein the lower portion comprises a portion of a metal layer.

7. The method of claim 5, wherein the middle portion comprises a portion of a doped semiconductor layer.

8. The method of claim 7, wherein the doped semiconductor layer is one of a polycrystalline silicon layer or a silicon-germanium layer.

9. The method of claim 1, wherein forming the gate stack comprises:

forming the lower portion of the gate stack with a layer of a metal or a metal alloy and a doped polysilicon layer; and

forming the middle portion of the gate stack with a doped polycrystalline silicon-germanium layer.

10. The method of claim 1, wherein forming the gate stack comprises:

forming the lower portion of the gate stack with a layer of a first metal or metal alloy; and

forming the middle portion of the gate stack with a layer of a second metal or metal alloy.

11. A method for manufacturing a MOS transistor comprising:

forming a gate stack having a height, a length, and a width and comprising a lower portion, a middle portion and an upper portion;

forming around the gate stack a first spacer surrounded with another material;

removing the first spacer to form a cavity in said another material;

reducing a length of the middle portion of the gate stack in said cavity relative to the lengths of the lower and upper portions;

lining side walls of the cavity and the gate stack with an insulating material;

closing an upper aperture of the cavity so as to provide an air spacer defined by the lined side walls;

removing the gate stack to provide a gate stack opening; and

filling the gate stack opening with a conductive metal to form a metal gate having a lower conductive portion, a middle conductive portion and an upper conductive portion, wherein the length of the middle conductive portion is less than the lengths of the lower and upper conductive portions.

12. The method of claim 11, wherein forming the gate stack comprises:

forming the lower portion of the gate stack with at least one layer of a metal material; and

forming the middle portion of the gate stack with a portion of a doped semiconductor layer, said doped semiconductor layer comprising one of a polycrystalline silicon layer or a silicon-germanium layer.

13. The method of claim 11, wherein forming the gate stack comprises:

forming the lower portion of the gate stack with a layer of a metal or a metal alloy and a doped polysilicon layer; and

forming the middle portion with of the gate stack with a doped polycrystalline silicon-germanium layer.

14. The method of claim 11, wherein forming the gate stack comprises:

forming the lower portion of the gate stack with a layer of a first metal or metal alloy; and

forming the middle portion of the gate stack with a layer of a second metal or metal alloy.

15. The method of claim 11, wherein reducing the length of the middle portion of the gate stack in said cavity comprises etching material of the middle portion at a rate faster than the materials of the lower and upper portions.