Dual trench rectifier and method for forming the same

• US 9,117,902 B2
• Filed: 08/01/2013
• Issued: 08/25/2015
• Est. Priority Date: 08/01/2013
• Status: Active Grant

• Current Assignee: Qinhai Jin
• Original Assignee: Chip Integration Tech. Co., Ltd.
• Inventors: Jin, Qinhai
• Primary Examiner(s): Tran, Tran
• Application Number:
  US13/956,474
• Publication Number:
  US 20150035047A1
• Time in Patent Office: 754 Days
• Field of Search: 257328-330
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0814 Diodes only
• CPC Class Codes: H01L 29/0607 for preventing surface leakage or controlling electric field concentration
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A structure of dual trench rectifier comprises of the following elements. A plurality of trenches are formed parallel in an n− epitaxial layer on an n+ semiconductor substrate and spaced with each other by a mesa. A plurality of recesses are formed on the mesas. Each the trench has a trench oxide layer formed on the sidewalls and bottom thereof, and a first poly silicon layer is filled therein to form MOS structures. Each the recess has a recess oxide layer formed on the sidewalls and bottom thereof, and a second poly silicon layer is filled therein to form MOS structures. A plurality of p type bodies are formed at two sides of the MOS structures in recesses. A top metal is formed above the semiconductor substrate for serving as an anode. A bottom metal is formed beneath the semiconductor substrate for serving as a cathode.

Claims

1. A dual trench rectifier comprising of:

a plurality of trenches formed in parallel in an n−

epitaxial layer on a heavy doped n+ semiconductor substrate, wherein the trenches each has a trench oxide layer formed on a bottom and sidewalls thereof;

a plurality of recesses formed in the n−

epitaxial layer at mesas between the plurality of trenches, wherein the recesses each has a recess oxide layer formed on a bottom and sidewalls thereof;

a first polysilicon layer doped with conductive impurities formed and filled in the plurality of trenches;

a second polysilicon layer doped with conductive impurities formed and filled in the plurality of recesses;

a plurality of p type bodies formed in the n−

epitaxial layer at the mesas, wherein said p type bodies each is interlaced with the recesses each along a longitudinal direction of the trenches;

a top metal layer formed on and contacted the first and second polysilicon layers and the mesas for serving as an anode, and a bottom metal layer formed beneath the heavy doped n+ semiconductor substrate for serving as a cathode.

2. The dual trench rectifier of claim 1, wherein each the p type body includes two n+ ion implanted areas individually adjacent to two sides of the MOS structures.

3. The dual trench rectifier of claim 1, further comprising a metal silicide layer formed in between the second polysilicon layer and the top metal layer and formed in between the n- epitaxial layer and the top metal layer.

4. A dual trench rectifier comprising of:

a plurality of trenches formed in parallel in an n−

epitaxial layer on a heavy doped n+ semiconductor substrate, wherein the trenches each has a trench oxide layer formed on a bottom and sidewalls thereof;

a plurality of recesses formed in the n−

epitaxial layer at mesas between the plurality of trenches, wherein the recesses each has a recess oxide layer formed on a bottom and sidewalls thereof and the recesses abutting the trench oxide layer of the trenches;

a first polysilicon layer doped with conductive impurities formed and filled in the plurality of trenches;

a second polysilicon layer doped with a conductive impurities formed and filled in the plurality of recesses;

a plurality of p type bodies formed in the n−

epitaxial layer at the mesas, wherein said p type bodies each is interlaced with the recesses each along a longitudinal direction of the trenches;

a top metal layer formed on and contacted the first and second polysilicon layers and the mesas for serving as an anode, and a bottom metal layer formed beneath the heavy doped n+ semiconductor substrate for serving as a cathode.

5. The dual trench rectifier of claim 4, wherein the p bodies abutting the trench oxide layer of the trenches.