Methods for managing alignment and latency in interference suppression
First Claim
Patent Images
1. A chipset for receiving a signal, the chipset comprising:
- a front end configured to receive a signal;
an analog-to-digital converter configured to sample the signal at a sample rate that is greater than or equal to a chipping rate to produce sample-rate data;
a downsampler configured to convert sample-rate data to a chipping rate to create chip-level data;
a symbol estimator configured to operate on chip-level data to create symbol-level data;
a post-processor configured to operate on symbol-level data to produce modified symbol-level data;
a respreader configured to apply a spreading code to the modified symbol-level data to create chip-level data indicative of a plurality of chip-level interference estimates; and
an interpolator configured to interpolate the chip-level data to create sample-level data indicative of a plurality of sample-level interference estimates.
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Abstract
An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data.
Various techniques may be employed for controlling the latency and sequencing of these operations, and the subsystems within the canceller may use different processing clock speeds.
156 Citations
18 Claims
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1. A chipset for receiving a signal, the chipset comprising:
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a front end configured to receive a signal; an analog-to-digital converter configured to sample the signal at a sample rate that is greater than or equal to a chipping rate to produce sample-rate data; a downsampler configured to convert sample-rate data to a chipping rate to create chip-level data; a symbol estimator configured to operate on chip-level data to create symbol-level data; a post-processor configured to operate on symbol-level data to produce modified symbol-level data; a respreader configured to apply a spreading code to the modified symbol-level data to create chip-level data indicative of a plurality of chip-level interference estimates; and an interpolator configured to interpolate the chip-level data to create sample-level data indicative of a plurality of sample-level interference estimates. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method, comprising:
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receiving a signal with a front end of a receiver; sampling the signal, with an analog-to-digital converter, at a sample rate that is greater than or equal to a chipping rate to produce sample-rate data; downsampling the sample-rate data to a chipping rate to create chip-level data; estimating symbol-level data based on the chip-level data; operating on the symbol-level data to produce modified symbol-level data; applying a spreading code to the modified symbol-level data to create chip-level data indicative of a plurality of chip-level interference estimates; and interpolating the chip-level data to create sample-level data indicative of a plurality of sample-level interference estimates. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A non-transitory computer readable storage medium, comprising a plurality of instructions, that in response to being executed, result in a receiver:
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sampling a signal at a sample rate that is greater than or equal to a chipping rate to produce sample-rate data; downsampling the sample-rate data to a chipping rate to create chip-level data; estimating symbol-level data based on the chip-level data; operating on the symbol-level data to produce modified symbol-level data; applying a spreading code to the modified symbol-level data to create chip-level data indicative of a plurality of chip-level interference estimates; and interpolating the chip-level data to create sample-level data indicative of a plurality of sample-level interference estimates. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification