Adaptive reference tuning for endurance enhancement of non-volatile memories

• US 9,122,404 B2
• Filed: 03/15/2013
• Issued: 09/01/2015
• Est. Priority Date: 03/15/2013
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dai, Bing, Lam, Chung H., Li, Jing
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US13/842,375
• Publication Number:
  US 20140281294A1
• Time in Patent Office: 900 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

Claims

1. A memory device comprising:

a plurality of memory cells;

a sensing circuit for determining a state of a selected memory cell among said plurality of memory cells, said state determining including measuring a physical quantity employed in detecting a bit value of the selected memory cell, said memory cell subject to plural write cycles applied to that memory cell; and

a memory controller comprising at least a control logic block and a look-up table, the look-up table for encoding a relationship between a value of a variable reference parameter value associated with measuring said physical quantity at said cell and a number of subjected said write cycles to said plurality of memory cells, and wherein said control logic block counts said plural write cycles to memory cell locations and determines an estimated number of cycling for said plurality of memory cells by counting a total number of cycling for at least one memory cell,

wherein for said cell memory state determining, said look-up table returns a value for said variable reference parameter to said sensing circuit for each value of said total number of cycling provided by said control logic block, and

said sensing circuit comparing a value of a measured quantity from said selected memory cell with the variable reference parameter in the determining of the cell state.

2. The memory device of claim 1, wherein said memory controller further comprises a wear leveling circuit that randomizes location of data written into said plurality of memory cells.

3. The memory device of claim 1, wherein said at least one memory cell is a single memory cell among said plurality of memory cells, and said estimated number of cycling is the same as a total number of cycling for said single memory cell.

4. The memory device of claim 1, wherein said at least one memory cell comprises a predetermined number of memory cells in which said number is in a range from 2 to 128, and said estimated number of cycling is a statistical quantity derived from a number of total cycles corresponding to said predetermined number of memory cells.

5. The memory device of claim 4, wherein said statistical quantity is a mathematical average of said number of total cycles corresponding to said predetermined number of cells.

6. The memory device of claim 1, wherein said look-up table stores encoded data for said value for said variable reference parameter for any positive integer value of said estimated number of cycling.

7. The memory device of claim 6, wherein said look-up table comprises:

first encoded memory cells storing a plurality of ranges for said estimated number of cycling; and

second encoded memory cells storing a set of values for said variable reference parameter, wherein each value among said set of values corresponds to a single range among said plurality of ranges for said estimated number of cycling.

8. The memory device of claim 7, wherein said plurality of ranges for said estimated number of cycling and said set of values for said variable reference parameter are a digitized approximation of a predefined function representing a cycling-dependent shift of a threshold value for said measured quantity for distinguishing a “

1”

state from a “

0”

state.

9. The memory device of claim 1, wherein said control logic block comprises a sensing reference mode register that identifies a mode of operation among a plurality of modes of operation of said plurality of memory cells.

10. The memory device of claim 1, wherein said variable reference parameter is a variable reference voltage, and said measured quantity is a voltage generated from a measurement on said selected memory cell.

11. The memory device of claim 1, wherein said variable reference parameter is a variable reference current, and said measured quantity is a current generated from a measurement on said selected memory cell.

12. The memory device of claim 1, wherein said variable reference parameter is a variable reference timing, and said measured quantity is a resistance generated from a measurement on said selected memory cell.

13. The memory device of claim 1, wherein said plurality of memory cells is a plurality of non-volatile memory cells.