Memory devices having special mode access

• US 9,122,420 B2
• Filed: 03/31/2014
• Issued: 09/01/2015
• Est. Priority Date: 10/17/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pekny, Theodore T., Tsai, Victor Y.
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US14/231,393
• Publication Number:
  US 20140215139A1
• Time in Patent Office: 519 Days
• Field of Search: 365/185.08, 365/185.09, 365/185.12, 365/185.17, 365/185.33, 365/233.1, 365/238.5, 365/240
• US Class Current: 1/1
• CPC Class Codes: G06F 12/145 the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 2212/1052 Security improvement
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A memory device includes a memory array, a special mode enable register, and a controller. When the controller receives a register write command to write first data into the special mode enable register and the memory device does so, the memory device operates in a first mode. When the controller receives a register write command to write second data into the special mode enable register and the memory device does so, the memory device operates in a second mode.

Claims

1. A memory device comprising:

a memory array;

a special mode enable register; and

a controller configured to receive, from a host device, a register write command, wherein;

when the register write command instructs the memory device to write a first data into the special mode enable register and the first data is written into the special mode enable register, the memory device is configured to operate in a first mode; and

when the register write command instructs the memory device to write a second data into the special mode enable register and the second data is written into the special mode enable register, the memory device is configured to operate in a second mode.

2. The memory device of claim 1, wherein the special mode enable register comprises a parameter page enable component comprising one or more bits configured to enable or disable access to a parameter page of the memory array.

3. The memory device of claim 2, wherein the first data is configured to, when written to the special mode enable register, cause the parameter page enable component to contain data that causes the memory device to operate in the first mode, wherein the first mode is configured to cause the memory device to permit access to the parameter page via a first command.

4. The memory device of claim 3, wherein the second data is configured to, when written to the special mode enable register, cause the parameter page enable component to contain data that causes the memory device to operate in the second mode, wherein the second mode is configured to cause the memory device not to permit access to the parameter page via the first command.

5. The memory device of claim 1, wherein the special mode enable register comprises a parameter page enable bit that is configured to be set by the first data and reset by the second data and that, when set, is configured to cause the memory device to operate in the first mode and, when reset, is configured to cause the memory device to operate in the second mode, wherein:

the first mode is configured to cause the memory device to permit access to the parameter page; and

the second mode is configured to cause the memory device not to permit access to the parameter page.

6. The memory device of claim 1, wherein the special mode enable register comprises a block lock writing register that, when written to with the first data, is configured to cause the memory device to operate in the first mode and, when written to with the second data, is configured to cause the memory device to operate in the second mode, wherein:

the first mode is configured to cause the memory device not to permit access to one or more portions of the memory array; and

the second mode is configured to cause the memory device to permit access to the one or more portions of the memory array.

7. The memory device of claim 1, wherein:

the memory array comprises a one time programmable (OTP) block;

the special mode enable register comprises an OTP enable component comprising one or more bits configured to enable an OTP operating mode in which the memory device is enabled to access the OTP block.

8. The memory device of claim 7, wherein the special mode enable register comprises an OTP lock component comprising one or more bits configured to allow or disallow writing to the OTP block.

9. The memory device of claim 1, wherein the controller is configured to receive the register write command via a serial interface.

10. The memory device of claim 1, wherein the special mode enable register is configured to control an output buffer drive strength, a desired number of clock cycles of latency for outputting data, an address cycle format to require whole bytes or to use a minimum number of addresses, whether to enable or disable error correcting codes (ECC), or any combination thereof.

11. The memory device of claim 1, wherein the special mode enable register is configured to enable switching between an SPI NAND and an NAND mode.