Retrieving boot instructions from nonvolatile memory

• US 9,122,493 B2
• Filed: 08/01/2014
• Issued: 09/01/2015
• Est. Priority Date: 04/10/2006
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wu, Stephen
• Primary Examiner(s): Cao, Chun
• Application Number:
  US14/449,365
• Publication Number:
  US 20140344564A1
• Time in Patent Office: 396 Days
• Field of Search: 713/1, 713/2
• US Class Current: 1/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/44573 Execute-in-place [XIP]

Abstract

Systems and processes for booting a device can be implemented by detecting a reset signal associated with the device and retrieving a predetermined page of data from a nonvolatile memory location into a register associated with the nonvolatile memory. The nonvolatile memory may be designed and implemented such that each page of data is retrieved from the nonvolatile memory as a unit, and the page of data includes instructions for use in booting the device. A command to read data stored in the register is received, and the command can include an address identifying a location of one or more instructions within the register. In response, the one or more instructions are retrieved from the register for execution by a processor.

Claims

1. A method for booting a computing device, the method comprising:

detecting a reset signal by a non-volatile memory die, wherein the non-volatile memory die includes an internal controller, a register, and non-volatile memory, and wherein the non-volatile memory includes a plurality of pages of data;

retrieving, by the internal controller, a predetermined page of data from the non-volatile memory responsive to detecting the reset signal, wherein each of the plurality of pages of data is retrieved from the non-volatile memory as a unit and the predetermined page of data includes at least one instruction for booting the computing device;

storing, by the internal controller, the predetermined page of data into the register;

fetching, by a host processor, the at least one instruction from the register using at least one simple read command, wherein the simple read command includes an address for randomly accessing locations within the predetermined page of data;

executing the at least one instruction by the host processor; and

fetching, by the host processor, a second page of data from the non-volatile memory using a read command, wherein the read command retrieves the second page of data, and wherein the second page of data is different from the predetermined page of data.

2. The method of claim 1, wherein the non-volatile memory comprises a NAND flash memory.

3. The method of claim 1, wherein retrieving the predetermined page of data is performed automatically in response to detecting the reset signal.

4. The method of claim 1, further comprising fetching a plurality of instructions from the register, wherein the plurality of instructions, when executed by the host processor, cause the host processor to read boot loader code from the non-volatile memory and store the boot loader code in a random access memory.

5. The method of claim 4, wherein the boot loader code includes instructions for copying operating system code or application code from the non-volatile memory to the random access memory.

6. The method of claim 1, further comprising reading at random, by the host processor, data stored at any address in the register.

7. The method of claim 4, wherein a given instruction of the plurality of instructions includes information regarding an address of a next instruction to be fetched from the plurality of instructions.

8. An apparatus comprising:

a plurality of non-volatile memory blocks, wherein each memory block includes a plurality of pages of data, wherein each of the plurality of pages of data is retrieved from a respective non-volatile memory block as a unit;

a register configured to store at least a page of data; and

circuitry configured to;

detect a reset signal;

retrieve a predetermined page of data from a first non-volatile memory block of the plurality of non-volatile memory blocks responsive to detecting the reset signal, wherein the predetermined page of data includes at least one instruction for booting the host processor; and

store the predetermined page of data including the at least one instruction in the register;

wherein the register is further configured to provide the at least one instruction to the host processor responsive to receiving at least one simple read command from the host processor, wherein the simple read command includes an address for randomly accessing locations within the predetermined page of data; and

wherein the circuitry is further configured to;

retrieve a second page of data from a second non-volatile memory block in response to receiving a read command from the host processor, wherein the read command retrieves the second page of data, and wherein the second page of data is different from the predetermined page of data; and

sending the second page of data to the host processor.

9. The apparatus of claim 8, wherein the plurality of non-volatile memory blocks comprises a plurality of NAND flash memory blocks.

10. The apparatus of claim 8, wherein the circuitry is further configured to retrieve the predetermined page of data automatically in response to detecting the reset signal.

11. The apparatus of claim 8, wherein the predetermined page of data includes a plurality of instructions for the host processor.

12. The apparatus of claim 11, wherein a given instruction of the plurality of instructions includes information regarding an address of a next instruction to be provided from the plurality of instructions.

13. The apparatus of claim 8, wherein the register is configured to enable random access to data stored at any address in the register in response to a given read command from the host processor.

14. A system comprising:

a host processor; and

a non-volatile memory device, separate from the host processor, wherein the non-volatile memory device includes;

one or more non-volatile memory blocks, wherein each memory block includes a plurality of pages of data, wherein each of the plurality of pages of data is retrieved from a respective non-volatile memory block as a unit; and

a register;

wherein the non-volatile memory device is configured to;

detect a reset signal;

retrieve a predetermined page of data from a first non-volatile memory block responsive to detecting the reset signal, wherein the predetermined page of data includes at least one instruction for booting the host processor; and

store the predetermined page of data including the at least one instruction in the register;

wherein the host processor is configured to;

fetch the at least one instruction from the register using at least one simple read command, wherein the simple read command includes an address for randomly accessing locations within the predetermined page of data; and

execute the at least one instruction;

fetch a second page of data from a second non-volatile memory block using a read command, wherein the read command retrieves the second page of data, and wherein the second page of data is different from the predetermined page of data.

15. The system of claim 14, wherein the non-volatile memory device comprises a NAND flash memory device.

16. The system of claim 14, wherein the non-volatile memory device is further configured to retrieve the predetermined page of data automatically in response to detecting the reset signal.

17. The system of claim 14, further comprising a random access memory, wherein the host processor is further configured to fetch a plurality of instructions from the register, wherein the fetched instructions cause the host processor to read boot loader code from the non-volatile memory device and store the boot loader code in the random access memory.

18. The system of claim 17, wherein the boot loader code includes instructions for copying operating system code or application code from the non-volatile memory device to the random access memory.

19. The system of claim 14, wherein the non-volatile memory device is configured to enable random access to data stored at any address in the register in response to a read command from the host processor.

20. The system of claim 14, wherein the host processor is further configured to convert an instruction fetch command into at least one command to read data from the register.