Pseudo cache memory in a multi-core processor (MCP)

• US 9,122,617 B2
• Filed: 11/21/2008
• Issued: 09/01/2015
• Est. Priority Date: 11/21/2008
• Status: Expired due to Fees

• Current Assignee: Kyndryl Incorporated
• Original Assignee: International Business Machines Corporation
• Inventors: Duvalsaint, Karl J., Kim, Daeik, Kim, Moon J.
• Primary Examiner(s): Tseng, Cheng-Yuan
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/276,069
• Publication Number:
  US 20100131712A1
• Time in Patent Office: 2,475 Days
• Field of Search: 711/130, 711/117, 711/118, 711/148, 709/213
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

Specifically, under the present invention, a cache memory unit can be designated as a pseudo cache memory unit for another cache memory unit within a common hierarchal level. For example, in case of cache miss at cache memory unit “X” on cache level L2 of a hierarchy, a request is sent to a cache memory unit on cache level L3 (external), as well as one or more other cache memory units on cache level L2. The L2 level cache memory units return search results as a hit or a miss. They typically do not search L3 nor write back with the L3 result even (e.g., if it the result is a miss). To this extent, only the immediate origin of the request is written back with L3 results, if all L2s miss. As such, the other L2 level cache memory units serve the original L2 cache memory unit as pseudo caches.

Claims

1. A pseudo memory system, comprising:

a first memory unit mounted on a bus;

a first manager coupled to an input and an output of the first memory unit; and

a second memory unit mounted on the bus, the second memory unit being on a common hierarchical level with the first memory unit and the first cache manager being configured to;

designate a the memory block of the second memory unit as a pseudo memory unit for the first memory unit,

receive a request, and send the request simultaneously to a third memory unit located externally on a higher hierarchical level than the common hierarchical level and to the memory block of the second memory unit, and

enable the second memory unit to function as a next-level higher cache to the first memory unit following a cache memory miss on the common hierarchical level.

2. The pseudo memory system of claim 1, the first memory unit and the second memory unit comprising virtualized cache memory units, and the first manager being a cache manager.

3. The pseudo memory system of claim 1, further comprising a second manager coupled to the second memory unit, the second manager being operable to receive the request from the first cache manager, send the request to the second memory unit, and configure the second memory unit to act as a pseudo memory unit for the first memory unit.

4. The pseudo memory system of claim 3, further comprising:

a first set of sub-memory units coupled to the first manager; and

a first set of sub-processing elements coupled to the first set of sub-memory units.

5. The pseudo memory system of claim 4, further comprising:

a second set of sub-memory units coupled to the second manager; and

a second set of sub-processing elements coupled to the second set of sub-memory units.

6. The pseudo memory system of claim 1, the bus being coupled to a main controller.

7. The pseudo memory system of claim 1, the first manager being further coupled to the bus.

8. The pseudo memory system of claim 7, the third memory unit also coupled to the bus.

9. A pseudo cache memory system, comprising:

a first cache memory unit coupled to a bus;

a first cache manager coupled to an input and an output of the first cache memory unit, and

a second cache manager coupled to an input and an output of the second cache memory unit; and

a second set of sub-cache memory units coupled to the second cache manager,

wherein the first cache manager is operable to;

designate a memory block of the second cache memory unit as a pseudo cache memory unit of the first cache memory unit to enable the second memory unit to function as a next-level higher cache to the first memory unit,

receive a request, and

simultaneously send the request to the memory block of a second cache memory unit and to a third memory unit located externally on a higher hierarchical level than a common hierarchical level of the first cache memory unit and the second cache memory unit, wherein the request is simultaneously sent following a cache memory miss on the common hierarchical level, wherein the second cache memory unit is coupled to the bus, a first set of sub-cache memory units coupled to the first cache manager.

10. The pseudo cache memory system of claim 9, further comprising a first set of sub-processing elements coupled to the first set of sub-cache memory units.

11. The pseudo cache memory system of claim 9, further comprising a second set of sub-processing elements coupled to the second set of sub-cache memory units.

12. The pseudo cache memory system of claim 9, the bus being coupled to a main controller.

13. The pseudo cache memory system of claim 9, the second cache manager being operable to designate another cache memory unit in the common hierarchy as a pseudo cache memory unit of the second cache memory unit.

14. A pseudo cache memory method, comprising:

receiving a request on a first cache manager, the first cache manager being coupled to an input and an output of a first memory unit, the first cache memory unit being coupled to a bus;

designating a memory block of a second cache memory unit as a pseudo cache memory unit of the first cache memory unit, the second cache memory unit also being coupled to the bus, the second cache memory unit being in a common hierarchical level as the first cache memory unit; and

sending the request simultaneously to the pseudo cache memory unit and a third cache memory unit located externally on a higher hierarchical level than a common hierarchical level of the first cache memory unit and the second cache memory unit, wherein the request is sent simultaneously following a cache memory miss on the common hierarchical level to enable the second memory unit to function as a next-level higher cache to the first memory unit.

15. The pseudo cache memory method of claim 14, the request being received from a first set of sub-memory units coupled to the first cache memory unit.

16. The memory pseudo method of claim 14, further comprising:

receiving the request on second cache manager coupled to the pseudo cache memory unit; and

processing the result using the pseudo cache memory unit.

17. The pseudo cache memory method of claim 14, further comprising sending a result of the processing to the first cache memory unit.

18. The pseudo cache memory method of claim 14, the third cache memory unit is coupled to the bus.