Performing a histogram using an array of addressable registers
First Claim
Patent Images
1. A method for parallel processing of an image using processing circuitry including an array of addressable registers, the method comprising:
- extracting a plurality of image features from the image, wherein the image features are storable as data;
according to respective values of a sorting key, wherein said sorting key is derived from at least one parameter of the data, sorting the image features into a plurality of N buckets; and
using an array of M addressable registers, where M is less than N, according to values of a histogram key derived from said at least one parameter of the data, summing said data within said buckets thereby performing a histogram of the image features.
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Abstract
Parallel processing of an image using an array of addressable registers. Image features are extracted from the image. The image features are storable as data. According to respective values of a sorting key derived from a parameter of the data, the image features are sorted into N buckets. Using an array of M addressable registers, where M is less than N, the data are summed within the buckets to perform a histogram of the image features, according to values of a histogram key derived from said a parameter of the data.
107 Citations
10 Claims
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1. A method for parallel processing of an image using processing circuitry including an array of addressable registers, the method comprising:
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extracting a plurality of image features from the image, wherein the image features are storable as data; according to respective values of a sorting key, wherein said sorting key is derived from at least one parameter of the data, sorting the image features into a plurality of N buckets; and using an array of M addressable registers, where M is less than N, according to values of a histogram key derived from said at least one parameter of the data, summing said data within said buckets thereby performing a histogram of the image features. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification