Method for managing the operation of a memory device having a SRAM memory plane and a non volatile memory plane, and corresponding memory device

• US 9,123,413 B2
• Filed: 06/26/2014
• Issued: 09/01/2015
• Est. Priority Date: 07/09/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Tailliet, Franois, Battista, Marc
• Primary Examiner(s): DINH, SON T
• Application Number:
  US14/315,401
• Publication Number:
  US 20150016188A1
• Time in Patent Office: 432 Days
• Field of Search: 365/185.08, 365/154, 365/189.14, 365/189.15, 365/189.16
• US Class Current: 1/1
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.

Claims

1. A method for managing the operation of a memory cell that comprises an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another, the method comprising:

transferring a data bit between the SRAM elementary memory cell and the non-volatile elementary memory cell;

storing a control datum in a control memory cell that is functionally analogous to and associated with the memory cell;

reading the data bit from the SRAM elementary memory cell;

performing a corresponding read of the control datum; and

inverting the data bit read from the SRAM elementary memory cell if the control datum has a first value while not inverting the data bit read from the SRAM elementary memory cell if the control datum has a second value.

2. The method according to claim 1, wherein transferring the data bit between the SRAM elementary memory cell and the non-volatile elementary memory cell comprises transferring the data bit from the SRAM elementary memory cell to the non-volatile elementary memory cell.

3. The method according to claim 1, wherein transferring the data bit between the SRAM elementary memory cell and the non-volatile elementary memory cell comprises transferring the data bit from the non-volatile elementary memory cell to the SRAM elementary memory cell.

4. The method according to claim 1, wherein the control datum has the first value when the data has been written to the SRAM elementary memory cell an odd number of times from the non-volatile memory cell since the SRAM elementary memory cell has been written to from a source external to the memory cell and wherein the control datum has the second value when the data has been written to the SRAM elementary memory cell an even number of times since the SRAM elementary memory cell has been written to from a source external to the memory cell.

5. The method according to claim 1, wherein the memory cell is one cell in a set that includes a plurality of blocks, each block including a plurality of memory cells, wherein a control memory cell is associated with each block of memory cells.

6. The method according to claim 5, wherein the control datum has the first value when the data has been written to the block of memory cells an odd number of times since the block of memory cells has been written to from a source external to the block, wherein the control datum has the second value when the data has been written to the block of memory cells an even number of times since the block of memory cells has been written to from a source external to the block, and wherein the inverting or not inverting is performed for each memory cell in the block of memory cells when the memory cells of the block are read.

7. The method according to claim 1, wherein the memory cell is one cell in a set that includes a plurality of subsets of a plurality of blocks of a plurality of memory cells, wherein a control memory cell is associated with each subset of blocks of memory cells, wherein the control datum has the first value when the data has been written to the subset of memory cells an odd number of times since the subset of memory cells has been written to from a source external to the block of memory cells, wherein the control datum has the second value when the data has been written to the subset of memory cells an even number of times since the subset of memory cells has been written to from a source external to the block of memory cells, and wherein the inverting or not inverting is performed for each memory cell in the subset of memory cells when the memory cells of the subset are read.

8. The method according to claim 7, wherein data of other SRAM elementary memory cells of other blocks of the subset are read and inverted read data is overwritten into these other SRAM elementary memory cells of the other blocks when datum from the subset of memory cells is inverted.

9. The method according to claim 1, wherein the first value is a logical value equal to 0 and the inverting or not inverting comprises applying an EXCLUSIVE OR logical function to the data bit read from the SRAM elementary memory cell and to the control datum read from the control memory cell.

10. The method according to claim 1, wherein the non-volatile elementary memory cell comprises an EEPROM cell.

11. A method for managing the operation of a set that includes a memory cell that comprises an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another, the memory cell being configured to carry out a datum value inversion in a reloading a datum previously written into the non-volatile elementary memory cell into the SRAM elementary memory cell, the method comprising:

with each transfer of a datum from the SRAM elementary memory cell into the non-volatile elementary memory cell and with each reloading of the SRAM elementary memory cell, performing the same operations on a control datum of a control memory cell that is functionally analogous to and associated with the memory cell; and

with each reading of a datum of the SRAM elementary memory cell, performing a corresponding reading of the control datum, and the datum read from the SRAM elementary memory cell being inverted or not according to the value read from the control datum.

12. The method according to claim 11, wherein

in a first writing of a datum into the SRAM elementary memory cell of the memory cell, following an odd number of reloading(s) of the SRAM elementary memory cell since the last writing into the SRAM elementary memory cell, writing the control datum having a first value into the control memory cell;

if a read control datum value is equal to a second value different from the first value, inverting the value of the datum of the SRAM elementary memory cell of the memory cell upon reading and delivering the inverted datum; and

if the read control datum is equal to the first value, delivering the datum read from the SRAM elementary memory cell of the memory cell with no inversion.

13. The method according to claim 12, further comprising, prior to writing the control datum having the first value into the control memory cell, reading the value of the control datum from the control memory cell, a read value of the control datum equal to the second value indicating that the writing of a datum into the SRAM elementary memory cell of a memory cell is a first writing following an odd number of reloading(s) since the last writing into the SRAM elementary memory cell.

14. The method according to claim 12, wherein the first value is a logical value equal to 0 and wherein delivering inverted or actual data comprises applying an EXCLUSIVE OR logical function to the datum read from each SRAM elementary memory cell and to the control datum read from the associated control memory cell.

15. The method according to claim 11, wherein the set includes a plurality of blocks of memory cells, wherein a control memory cell is associated with each block of memory cells;

wherein, in a first writing of a data block into a block of SRAM elementary memory cells of a corresponding block of memory cells, following an odd number of reloading(s) the block of SRAM elementary memory cells since the last writing into the block of SRAM elementary memory cells, the control datum having a first logical value is written into the associated control memory cell;

in response to a command to read contents of each SRAM elementary memory cell of the block, reading the control data of the associated control memory cell;

if the read value of the control datum is equal to a second value different from the first value, inverting the value of the datum of each SRAM elementary memory cell of the block is and delivering inverted datum; and

if the read value of the control datum is equal to the first value, delivering the datum actually read from each SRAM elementary memory cell of the block.

16. The method according to claim 11, wherein the set includes a plurality of subsets of a plurality of blocks of a plurality of memory cells, wherein a control memory cell is associated with each subset of blocks of memory cells;

wherein, in a first writing of a data block into a block of SRAM elementary memory cells of a subset of memory cells, following an odd number of reloading(s) of the subset of SRAM elementary memory cells since the last writing into the block of SRAM elementary memory cells of this subset, the control datum having a first logical value is written into the associated control memory cell, and the data of other SRAM elementary memory cells of the other blocks of the subset are read and the read but inverted data are overwritten into these other SRAM elementary memory cells of the other blocks;

in response to a command to read the contents of each SRAM elementary memory cell of the subset, reading the contents of the control memory;

if the read value of the control datum is equal to a second value different from the first value, inverting the value of the datum of each SRAM elementary memory cell of the subset and delivering each inverted datum; and

if the read value of the control datum is equal to the first value, delivering the datum actually read from each SRAM elementary memory cell of the subset.

17. The method according to claim 16, comprising, in response to each command to write at least one data block into at least one block of SRAM elementary memory cells of a subset of memory cells, reading the corresponding control datum;

if the control datum has the second value, writing of the data block into the at least one block of SRAM elementary memory cells of the subset of memory cells, writing the control datum having the first value into the associated control memory cell, reading the data of other SRAM elementary memory cells of the other blocks of the subset, and overwriting the read data with inverted read data into the other SRAM elementary memory cells of the other blocks; and

if the control datum has the first value, writing of the data block into the at least one block of SRAM elementary memory cells of the subset of memory cells.

18. The method according to claim 11, wherein the non-volatile elementary memory cell comprises an EEPROM cell.

19. A memory device, comprising:

a set that includes a plurality of memory cells, each memory cell including an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another;

a control memory cell that is functionally analogous to a first memory cell of the plurality of memory cells and is associated with the first memory cell;

a first processing circuit configured, with each transfer of a datum from the SRAM elementary memory cell into the non-volatile elementary memory cell of the first memory cell and with each reloading of the SRAM elementary memory cell of the first memory cell, to perform the same corresponding operations on a control datum of the control memory cell; and

a second processing circuit configured, with each reading of a datum from the SRAM elementary memory cell of the first memory cell, to carry out a corresponding reading of the control datum and to perform an inversion or not of the datum read from the SRAM elementary memory cell according to the read value of the control datum.

20. The device according to claim 19, further comprising a third processing circuit configured, in the first writing of a datum into the SRAM elementary memory cell of the first memory cell, following an odd number of reloading(s) of the SRAM elementary memory cell since the last writing into the SRAM elementary memory cell, to write the control datum having a first value into the SRAM elementary memory cell of the control memory cell;

wherein the second processing circuit is configured to read the contents of the control memory cell in response to a command to read the contents of the SRAM elementary memory cell of the at least one memory cell;

wherein, if the read value of the control datum is equal to a second value different from the first, the second processing circuit is configured to invert the value of the datum of the SRAM elementary memory cell of the first memory cell and to deliver the inverted datum; and

wherein, if the read value of the control datum is equal to the first value, the second processing circuit is configured to deliver the datum actually read from the SRAM elementary memory cell of the first memory cell.

21. The device according to claim 20, wherein the third processing circuit is configured, prior to writing of the control datum having the first value into the control memory cell, to read the value of the control datum from the control memory cell, a read value of the control datum equal to the second value indicating that the writing of a datum into the SRAM elementary memory cell of a memory cell is a first writing following an odd number of reloading(s) since the last writing into the SRAM elementary memory cell.

22. The device according to claim 20, wherein the first value is a logical value equal to 0 and wherein the second processing circuit comprises, for each SRAM elementary memory cell of each memory cell, an EXCLUSIVE OR logical operator configured to receive at the input the datum read from the SRAM elementary memory cell and the control datum read from the SRAM elementary memory cell of the associated control memory cell.

23. The device according to claim 19, wherein the set includes a plurality of blocks memory cells, a control memory cell being associated with each block of memory cells;

wherein the device further comprises a third processing circuit configured, in a first writing of a data block into a block of SRAM elementary memory cells of the corresponding block of memory cells, following an odd number of reloading(s) of the block of SRAM elementary memory cells since the last writing into the block of SRAM elementary memory cells, to write the control datum having a first logical value into the SRAM elementary memory cell of the associated control memory cell;

wherein the second processing circuit is configured to read the contents of the SRAM cell of the associated control memory cell in response to a command to read the contents of each SRAM elementary memory cell of the block;

wherein, if the read value of the control datum is equal to a second logical value different from the first, the second processing circuit is configured to invert the value of the datum of each SRAM elementary memory cell of the block and to deliver each inverted datum; and

wherein, if the read value of the control datum is equal to the first logical value, the second processing circuit is configured to deliver the datum actually read from each SRAM elementary memory cell of the block.

24. The device according to claim 19, wherein the set includes a plurality of subsets of a plurality of blocks of a plurality of memory cells, a control memory cell being associated with each subset of blocks of memory cells;

wherein the device further comprises a third processing circuit configured, in a first writing of at least one data block into at least one block of SRAM elementary memory cells of a subset of memory cells, following an odd number of reloading(s) of the subset of SRAM elementary memory cells since the last writing into at least one block of SRAM elementary memory cells of this subset, to write the control datum having a first logical value into the control memory cell, to read the data contained in the other SRAM elementary memory cells of the other blocks of the subset, and to overwrite the read but inverted data into these other SRAM elementary memory cells;

wherein the second processing circuit is configured to read the contents of the SRAM cell of the control memory cell in response to a command to read the contents of each SRAM elementary memory cell of the subset;

wherein, if the read value of the control datum is equal to a second logical value different from the first, the second processing circuit is configured to invert the value of the datum of each SRAM elementary memory cell of the subset and two deliver each inverted datum; and

wherein, if the read value of the control datum is equal to the first logical value, the second processing circuit is configured to deliver the datum actually read from each SRAM elementary memory cell of the subset.

25. The device according to claim 24, wherein the third processing circuit is configured to read the corresponding control datum, in response to each command to write at least one data block into at least one block of SRAM elementary memory cells of a subset of memory cells;

wherein, if the control datum has the second value, the second processing circuit is configured to write the data block into the at least one block of SRAM elementary memory cells of the subset of memory cells, to write the control datum having the first value into the SRAM elementary memory cell of the associated control memory cell, to read the data from the other SRAM elementary memory cells of the other blocks of the subset, and to overwrite the read with inverted read data into these other SRAM elementary memory cells of the other blocks; and

wherein, if the control datum has the first value, the second processing circuit is configured to write the data block into the at least one block of SRAM elementary memory cells of the subset of memory cells.

26. The device according to claim 19, wherein the SRAM elementary memory cell of each memory cell comprises two inverters cross-coupled to one another, wherein the non-volatile elementary memory cell of each memory cell comprises a floating-gate transistor connected between a power supply terminal and a first output of the two inverters, and wherein each memory cell further comprises an interconnect transistor coupled in series between the power supply terminal and the floating-gate transistor or between the floating-gate transistor and the first output of the two inverters.

27. The device according to claim 19, wherein the SRAM elementary memory cell of each memory cell comprises two inverters cross-coupled to one another, wherein each memory cell comprises a plurality of non-volatile elementary memory cells, each non-volatile elementary memory cell having a floating-gate transistor, the floating-gate transistors having first conduction electrodes connected to a power supply terminal and second conduction electrodes connected to the outputs of the two inverters via two interconnect transistors.

28. The device according to claim 19, wherein each non-volatile elementary memory cell comprises an EEPROM cell.