Method for managing the operation of a memory device having a SRAM memory plane and a non volatile memory plane, and corresponding memory device
First Claim
1. A method for managing the operation of a memory cell that comprises an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another, the method comprising:
- transferring a data bit between the SRAM elementary memory cell and the non-volatile elementary memory cell;
storing a control datum in a control memory cell that is functionally analogous to and associated with the memory cell;
reading the data bit from the SRAM elementary memory cell;
performing a corresponding read of the control datum; and
inverting the data bit read from the SRAM elementary memory cell if the control datum has a first value while not inverting the data bit read from the SRAM elementary memory cell if the control datum has a second value.
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Accused Products
Abstract
A method can be used for managing the operation of a memory cell that includes an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another. A data bit is transferred between the SRAM elementary memory cell and the non-volatile elementary memory cell. A control datum is stored in a control memory cell that is functionally analogous to and associated with the memory cell. The data bit is read from the SRAM elementary memory cell and a corresponding read of the control datum is performed. The data bit read from the SRAM elementary memory cell is inverted if the control datum has a first value but the data bit read from the SRAM elementary memory cell is not inverted if the control datum has a second value.
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Citations
28 Claims
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1. A method for managing the operation of a memory cell that comprises an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another, the method comprising:
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transferring a data bit between the SRAM elementary memory cell and the non-volatile elementary memory cell; storing a control datum in a control memory cell that is functionally analogous to and associated with the memory cell; reading the data bit from the SRAM elementary memory cell; performing a corresponding read of the control datum; and inverting the data bit read from the SRAM elementary memory cell if the control datum has a first value while not inverting the data bit read from the SRAM elementary memory cell if the control datum has a second value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for managing the operation of a set that includes a memory cell that comprises an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another, the memory cell being configured to carry out a datum value inversion in a reloading a datum previously written into the non-volatile elementary memory cell into the SRAM elementary memory cell, the method comprising:
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with each transfer of a datum from the SRAM elementary memory cell into the non-volatile elementary memory cell and with each reloading of the SRAM elementary memory cell, performing the same operations on a control datum of a control memory cell that is functionally analogous to and associated with the memory cell; and with each reading of a datum of the SRAM elementary memory cell, performing a corresponding reading of the control datum, and the datum read from the SRAM elementary memory cell being inverted or not according to the value read from the control datum. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A memory device, comprising:
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a set that includes a plurality of memory cells, each memory cell including an SRAM elementary memory cell and a non-volatile elementary memory cell coupled to one another; a control memory cell that is functionally analogous to a first memory cell of the plurality of memory cells and is associated with the first memory cell; a first processing circuit configured, with each transfer of a datum from the SRAM elementary memory cell into the non-volatile elementary memory cell of the first memory cell and with each reloading of the SRAM elementary memory cell of the first memory cell, to perform the same corresponding operations on a control datum of the control memory cell; and a second processing circuit configured, with each reading of a datum from the SRAM elementary memory cell of the first memory cell, to carry out a corresponding reading of the control datum and to perform an inversion or not of the datum read from the SRAM elementary memory cell according to the read value of the control datum. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28)
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Specification