Adjusting control gate overdrive of select gate transistors during programming of non-volatile memory

• US 9,123,425 B2
• Filed: 10/07/2013
• Issued: 09/01/2015
• Est. Priority Date: 04/02/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dong, Yingda, Higashitani, Masaaki
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US14/047,381
• Publication Number:
  US 20140293701A1
• Time in Patent Office: 694 Days
• Field of Search: 365/185.28
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a lower control gate overdrive voltage so that the channel potential under it is lower, and the next SGD transistor has a higher control gate overdrive voltage so that the channel potential under it is higher. The different control gate overdrive voltages can be provided by programming different threshold voltages, or by providing different control gates voltages, for the SGD transistors. Undesirable reductions in a Vsgd window due to drain-induced barrier lowering can be avoided.

Claims

1. A 3D stacked non-volatile memory device, comprising:

alternating dielectric layers and conductive layers in a stack;

a set of NAND strings formed in the stack, the set of NAND strings comprising one NAND string and another NAND string, the one NAND string comprising a source-end select gate transistor, a plurality of memory cells, a first drain-end select gate transistor and a second drain-end select gate transistor between the plurality of memory cells and the first drain-end select gate transistor, the another NAND string comprising a source-end select gate transistor, a plurality of memory cells, a first drain-end select gate transistor and a second drain-end select gate transistor between the a plurality of memory cells of the another NAND string and the first drain-end select gate transistor of the another NAND string, control gates of the first drain-end select gate transistors are connected to one another by one of the conductive layers, and control gates of the second drain-end select gate transistors are connected to one another by another of the conductive layers; and

a control circuit in communication with the stack, the control circuit is configured to apply a program pulse to a selected memory cell of the another NAND string and, during the program pulse;

to allow programming of the selected memory cell, provide the first and second drain-end select gate transistors of the another NAND string in a conductive state, and to inhibit programming in the one NAND string, provide the first and second drain-end select gate transistors of the one NAND string in a non-conductive state, while providing a control gate overdrive voltage of the first drain-end select gate transistors which is lower than a control gate overdrive voltage of the second drain-end select gate transistors, wherein for each select gate transistor of the first drain-end select gate transistors and the second drain-end select gate transistors, the control gate overdrive voltage is equal to Vgs−

Vth, where Vgs is a control gate voltage minus a source voltage and Vth is a threshold voltage.

2. The 3D stacked non-volatile memory device of claim 1, wherein:

the one NAND string comprises a channel; and

a discontinuous potential in the channel, between the first and second drain-end select gate transistors of the one NAND string, is formed due to the control gate overdrive voltage of the first drain-end select gate transistor of the one NAND string being lower than the control gate overdrive voltage of the second drain-end select gate transistor of the one NAND string, the channel potential is lower under the first drain-end select gate transistor of the one NAND string than under the second drain-end select gate transistor of the one NAND string.

3. The 3D stacked non-volatile memory device of claim 1, wherein:

the first drain-end select gate transistors have a lower control gate overdrive voltage than the second drain-end select gate transistors due to the control circuit providing, during the program pulse, a voltage on the control gates of the first drain-end select gate transistors which is lower than a voltage on the control gates of the second drain-end select gate transistors.

4. The 3D stacked non-volatile memory device of claim 3, wherein:

the threshold voltages of the first drain-end select gate transistors are equal to the threshold voltage of the second drain-end select gate transistors.

5. The 3D stacked non-volatile memory device of claim 1, wherein:

the first drain-end select gate transistors have a lower control gate overdrive voltage than the second drain-end select gate transistors due to the threshold voltage of the first drain-end select gate transistors being higher than the threshold voltage of the second drain-end select gate transistor.

6. The 3D stacked non-volatile memory device of claim 5, wherein:

the control circuit, during the program pulse, is configured to provide an equal voltage on the control gates of the first and second drain-end select gate transistors.

7. The 3D stacked non-volatile memory device of claim 6, wherein:

the control gates of the first drain-end select gate transistors are connected to the control gates of the second drain-end select gate transistors.

8. The 3D stacked non-volatile memory device of claim 1, wherein:

the one NAND string comprises a third drain-end select gate transistor, the third drain-end select gate transistor of the one NAND string is between the plurality of memory cells of the one NAND string and the second drain-end select gate transistor of the one NAND string; and

during the program pulse, the control circuit is configured to provide the third select gate transistor with a control gate overdrive voltage equal to or greater than the control gate overdrive voltage of the second drain-end select gate transistors.

9. The 3D stacked non-volatile memory device of claim 1, wherein:

the first and second drain-end select gate transistors have a common control gate length.

10. A method for programming in a 3D stacked non-volatile memory device comprising alternating dielectric layers and conductive layers in a stack, the method comprising:

allowing programming in a selected NAND string; and

inhibiting programming in an unselected NAND string during the allowing programming in the selected NAND string, wherein;

the unselected NAND string comprises a source-end select gate transistor, a plurality of memory cells, a first drain-end select gate transistor and a second drain-end select gate transistor between the plurality of memory cells and the first drain-end select gate transistor,

the selected NAND string comprises a source-end select gate transistor, a plurality of memory cells, a first drain-end select gate transistor and a second drain-end select gate transistor between the plurality of memory cells of the selected NAND string and the first drain-end select gate transistor of the selected NAND string,

control gates of the first drain-end select gate transistors are connected to one another by one of the conductive layers,

control gates of the second drain-end select gate transistors are connected to one another by another of the conductive layers,

the inhibiting programming comprises providing the first and second drain-end select gate transistors of the unselected NAND string in a non-conductive state while providing a control gate overdrive voltage of the first drain-end select gate transistors which is lower than a control gate overdrive voltage of the second drain-end select gate transistors, and

a threshold voltage of the first drain-end select gate transistors is higher than a threshold voltage of the second drain-end select gate transistors.

11. The method of claim 10, wherein:

the control gate overdrive voltage of the first drain-end select gate transistors is lower than the control gate overdrive voltage of the second drain-end select gate transistors by at least 0.5 V.

12. The method of claim 10, wherein:

the providing the control gate overdrive voltage of the first drain-end select gate transistors which is higher than the control gate overdrive voltage of the second drain-end select gate transistors, comprises providing a voltage on the control gates of the first drain-end select gate transistors which is equal to a voltage on the control gates of the second drain-end select gate transistors.

13. The method of claim 12, wherein:

the threshold voltages of the first and second drain-end select gate transistors are set by a programming process which occurs before the programming in the selected NAND string.

14. A 3D stacked non-volatile memory device, comprising:

alternating dielectric layers and conductive layers in a stack;

an unselected NAND string extending in the stack, the unselected NAND string is connected to a bit line and comprises first and second drain-end select gate transistors and a plurality of memory cells, the first and second drain-end select gate transistors are between the bit line and the plurality of memory cells, a threshold voltage of the first drain-end select gate transistor is higher than a threshold voltage of the second drain-end select gate transistor, the second drain-end select gate transistor is between the first drain-end select gate transistor and the plurality of memory cells, and the unselected NAND string comprises a channel which extends vertically in the stack; and

a control circuit in communication with the stack, the control circuit, to inhibit programming in the unselected NAND string during programming of a selected NAND string is configured to;

control the first and second drain-end select gate transistors to provide the first and second drain-end select gate transistors in a non-conductive state and provide a discontinuous potential in the channel between the first and second drain-end select gate transistors, wherein a portion of the channel directly adjacent to the first drain-end select gate transistor has a lower potential than a portion of the channel directly adjacent to the second drain-end select gate transistor.

15. The 3D stacked non-volatile memory device of claim 14, wherein:

the control circuit, to provide the discontinuous potential in the channel between the first and second drain-end select gate transistors, is configured to provide a control gate overdrive voltage of the first drain-end select gate transistor which is lower than a control gate overdrive voltage of the second drain-end select gate transistor.

16. The 3D stacked non-volatile memory device of claim 15, wherein:

the control gate overdrive voltage of the first drain-end select gate transistor is lower than the control gate overdrive voltage of the second drain-end select gate transistor by at least 0.5 V.

17. The 3D stacked non-volatile memory device of claim 14, wherein:

the control circuit, to provide the discontinuous potential in the channel between the first and second drain-end select gate transistors, is configured to provide a voltage on a control gate of the first drain-end select gate transistor which is lower than a voltage on a control gate of the second drain-end select gate transistor.

18. The 3D stacked non-volatile memory device of claim 14, wherein:

the control circuit, to provide the discontinuous potential in the channel between the first and second drain-end select gate transistors, is configured to provide a voltage on a control gate of the first drain-end select gate transistor which is equal to a voltage on a control gate of the second drain-end select gate transistor.