Complementary metal-oxide-semiconductor device comprising silicon and germanium and method for manufacturing thereof

• US 9,123,566 B2
• Filed: 07/03/2013
• Issued: 09/01/2015
• Est. Priority Date: 07/03/2012
• Status: Active Grant

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Mitard, Jerome, Witters, Liesbeth
• Primary Examiner(s): ENAD, CHRISTINE A
• Application Number:
  US13/935,324
• Publication Number:
  US 20140008730A1
• Time in Patent Office: 790 Days
• Field of Search: 257/369, 438/199
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed are complementary metal-oxide-semiconductor (CMOS) devices and methods of manufacturing such CMOS devices. In some embodiments, an example CMOS device may include a substrate, and a buffer layer formed on the substrate, where the buffer layer comprises Si_1-xGe_x, where x is less than 0.5. The example CMOS device may further include one or more pMOS channel layer elements, where each pMOS channel layer element comprises Si_1-yGe_y, and where y is greater than x. The example CMOS device may still further include one or more nMOS channel layer elements, where each nMOS channel layer element comprises Si_1-zGe_z, and where z is less than x. In some embodiments, the example CMOS device may be a fin field-effect transistor (FinFET) CMOS device and may further include a first fin structure including the pMOS channel layer element(s) and a second fin structure including the nMOS channel layer element(s).

Claims

1. A fin field-effect transistor (FinFET) complementary metal-oxide-semiconductor (CMOS) device, comprising:

a substrate;

a buffer layer formed on the substrate, wherein the buffer layer comprises Si_1-xGe_x, wherein x is greater than 0 and less than 0.5;

one or more pMOS channel layer elements formed on the buffer layer, wherein each pMOS channel layer element comprises Si_1-yGe_y, wherein y is greater than x;

one or more nMOS channel layer elements formed on the buffer layer, wherein each nMOS channel layer element comprises Si_1-zGe_z, wherein z is less than x;

a first fin structure comprising the one or more pMOS channel layer elements;

a second fin structure comprising the one or more nMOS channel layer elements; and

further comprising at least one of;

(i) a first elevated source-drain (E S/D) electrode formed adjacent to the one or more pMOS channel layer elements, wherein the first E S/D comprises Si_1-pGe_p, and wherein p is greater than x, and a second E S/D formed adjacent to the one or more pMOS channel layer elements, wherein the second E S/D comprises Si_1-kGe_k, and wherein k is greater than p;

or

(ii) a third elevated source-drain (E S/D) electrode formed adjacent to the one or more nMOS channel layer elements, wherein the first E S/D comprises Si_1-ppGe_pp, and wherein pp is less than x, and a fourth E S/D formed adjacent to the one or more nMOS channel layer elements, wherein the second E S/D comprises Si_1-kkGe_kk, and wherein kk is less than pp.

2. The FinFET CMOS device of claim 1, further comprising at least one of:

(i) a first replacement gate formed on the one or more pMOS channel elements;

or

(ii) a second replacement gate formed on the one or more nMOS channel elements.

3. A method, comprising:

providing a substrate;

forming a buffer layer on the substrate, wherein the buffer layer comprises Si_1-xGe_x, wherein x is greater than 0 and less than 0.5;

forming one or more pMOS channel layer elements on the buffer layer, wherein each pMOS channel layer element comprises Si_1-yGe_y, wherein y is greater than x;

forming one or more nMOS channel layer elements on the buffer layer, wherein each nMOS channel layer element comprises Si_1-zGe_z, wherein z is less than x; and

forming at least one of;

(i) a first elevated source-drain (E S/D) electrode adjacent to the one or more pMOS channel layer elements, wherein the first E S/D comprises Si_1-pGe_p, and wherein p is greater than x, and a second E S/D adjacent to the one or more pMOS channel layer elements, wherein the second E S/D comprises Si_1-kGe_k, and wherein k is greater than p;

or

(ii) a third elevated source-drain (E S/D) electrode adjacent to the one or more nMOS channel layer elements, wherein the first E S/D comprises Si_1-ppGe_pp, and wherein pp is less than x, and a fourth E S/D adjacent to the one or more nMOS channel layer elements, wherein the second E S/D comprises Si_1-kkGe_kk, and wherein kk is less than pp.

4. The method of claim 3, further comprising forming at least one of:

(i) a first replacement gate (RPG) formed on the one or more pMOS channel layer elements;

or

(ii) a second RPG formed on the one or more nMOS channel layer elements.

5. The method of claim 3, wherein x is between about 0.15 and about 0.45.