Encapsulation of closely spaced gate electrode structures

• US 9,123,568 B2
• Filed: 11/21/2013
• Issued: 09/01/2015
• Est. Priority Date: 12/21/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Baars, Peter, Carter, Richard, Wei, Andy
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US14/086,563
• Publication Number:
  US 20140077308A1
• Time in Patent Office: 649 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/28 Encapsulations, e.g. encapsulating layers, coatings, e.g. for protectionH01L23/552 takes precedence; insulating layers for contacts or interconnections H01L23/5329
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7847 using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.

Claims

1. A semiconductor device, comprising:

a plurality of NMOS transistor elements, wherein each of said plurality of NMOS transistor elements comprises a first gate electrode structure above a first active region of a semiconductor substrate, at least two of said plurality of first gate electrode structures comprise a first encapsulating stack, said first encapsulating stack comprises a first dielectric cap layer and a first sidewall spacer stack, and said first sidewall spacer stack comprises at least three dielectric material layers; and

a plurality of PMOS transistor elements, wherein each of said plurality of PMOS transistor elements comprises a second gate electrode structure above a second active region of said semiconductor substrate, at least two of said plurality of second gate electrode structures comprise a second encapsulating stack, said second encapsulating stack comprises a second dielectric cap layer and a second sidewall spacer stack, and said second sidewall spacer stack comprises at least three dielectric material layers, wherein each of said at least three dielectric material layers of said first and second sidewall spacer stacks comprise a same dielectric material.

2. The semiconductor device of claim 1, wherein said first and second dielectric cap layers comprise said same dielectric material.

3. The semiconductor device of claim 1, wherein a thickness of at least one of said first and second sidewall spacer stacks is approximately 10-16 nm.

4. The semiconductor device of claim 1, further comprising an additional dielectric material layer above at least one of each of said first and second cap layers of each of said plurality of first and second gate electrode structures, respectively.

5. The semiconductor device of claim 4, wherein a combined thickness of said at least one of said first and second cap layers and said additional dielectric material layer thereabove is approximately 35-40 nm.

6. The semiconductor device of claim 1, further comprising raised source and drain regions formed in an active region adjacent to at least one of said plurality of NMOS and PMOS transistor elements, said raised source and drain regions comprising an epitaxial semiconductor material.

7. The semiconductor device of claim 6, wherein at least one of said raised source and drain regions is formed in at least one cavity in said active region adjacent to said at least one of said plurality of NMOS and PMOS transistor elements.

16. The semiconductor device of claim 1, wherein said plurality of NMOS transistor elements have a first gate electrode pitch dimension, and said plurality of PMOS transistor elements have a second gate electrode pitch dimension.

17. The semiconductor device of claim 16, wherein at least one of said first and second gate electrode pitch dimensions is less than 100 nm.

18. The semiconductor device of claim 1, wherein said same dielectric material comprises silicon nitride.

19. The semiconductor device of claim 6, wherein said active region is said first active region, said plurality of transistor elements are NMOS transistor elements, and said epitaxial semiconductor material comprises at least one of silicon and carbon.

20. The semiconductor device of claim 6, wherein said active region is said second active region, said plurality of transistor elements are PMOS transistor elements, and said epitaxial semiconductor material comprises at least one of silicon and germanium.

8. A semiconductor device, comprising:

a first gate electrode structure above an active region of a semiconductor substrate;

a second gate electrode structure above said active region and adjacent to said first gate electrode structure, wherein each of said first and second gate electrode structures comprise;

a gate electrode material;

a dielectric cap layer above said gate electrode material;

a first dielectric layer adjacent to sidewalls of said gate electrode material;

a second dielectric layer on said first dielectric layer; and

a third dielectric layer on said second layer, wherein said first, second, and third dielectric layers comprise a same dielectric material, said third layer comprising a first horizontal portion above said active region between said first and second gate electrode structures, wherein said first horizontal portion comprises an opening that exposes said active region; and

a conductive material in said opening, wherein said conductive material contacts said exposed active region.

9. The semiconductor device of claim 8, wherein said first and second gate electrode structures have a pitch dimension less than 100 nm.

10. The semiconductor device of claim 8, wherein said dielectric cap layer comprises said same dielectric material.

11. The semiconductor device of claim 8, wherein said first dielectric layer is in direct contact with said sidewalls of said gate electrode material.

12. The semiconductor device of claim 11, wherein said same dielectric material comprises silicon nitride.

13. The semiconductor device of claim 8, wherein a combined thickness of said first, second and third dielectric layers is approximately 10-16 nm.

14. The semiconductor device of claim 8, wherein said third dielectric layer further comprises a second horizontal portion above said dielectric cap layer.

15. The semiconductor device of claim 14, wherein a combined thickness of said dielectric cap layer and said second horizontal portion of said third dielectric layer is approximately 35-40 nm.