Nanowire field-effect transistor and method for manufacturing same

• US 9,123,695 B2
• Filed: 03/11/2013
• Issued: 09/01/2015
• Est. Priority Date: 03/13/2012
• Status: Active Grant

• Current Assignee: Postech Academy-Industry Foundation
• Original Assignee: Postech Academy-Industry Foundation
• Inventors: Baek, ChangKi, Rim, TaiUk, Ko, MyungDong
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US14/385,450
• Publication Number:
  US 20150069330A1
• Time in Patent Office: 904 Days
• Field of Search: 257/9, 257/29, 257/43, 257/E29.245, 438/104, 438/142, 438/151
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/1025 Channel region of field-effect devices
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: Y10S 977/891 Vapor phase deposition
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

Provided are a nanowire field-effect transistor and a method for manufacturing the same. The nanowire field-effect transistor can enable a source region to be positioned, with respect to an asymmetrical nanowire channel, adjacent to a region in which the diameter of the nanowire channel is large, can enable a drain region to be positioned adjacent to a region in which the diameter of the nanowire channel is small, can enable an ON current to be increased in a state in which a threshold voltage level is kept the same, and can enable the current drivability of a gate electrode to be improved.

Claims

1. A nanowire field-effect transistor comprising:

an asymmetrical nanowire channel whose both ends have mutually different diameters;

a source region that is adjacent to a region in which the diameter of the nanowire channel is large;

a drain region that is adjacent to a region in which the diameter of the nanowire channel is small;

a gate electrode that encloses the nanowire channel; and

a gate insulation film that is positioned between the nanowire channel and the gate electrode.

2. The nanowire field-effect transistor according to claim 1, wherein the diameter of the asymmetrical nanowire channel is reduced from the source region toward the drain region.

3. The nanowire field-effect transistor according to claim 1, further comprising

a substrate that is disposed adjacent to the source region.

4. The nanowire field-effect transistor according to claim 3, wherein the nanowire channel is formed vertically to the substrate.

5. The nanowire field-effect transistor according to claim 1, wherein the asymmetrical nanowire channel is made of silicon.

6. The nanowire field-effect transistor according to claim 1, wherein the diameter of the asymmetrical nanowire channel is 5 nm to 1 μ

m.

7. The nanowire field-effect transistor according to claim 1, wherein the same impurities are introduced to the source region and the drain region, and concentrations of the introduced impurities are mutually different.

8. The nanowire field-effect transistor according to claim 7, wherein the concentration of the impurities introduced to the drain region is higher than the concentration of the impurities introduced to the source region.

9. The nanowire field-effect transistor according to claim 7, wherein the impurities are boron (B), boron difluoride (BF₂), phosphorus (P), arsenic (As), or antimony (Sb).

10. A method for manufacturing a nanowire field-effect transistor comprising:

forming an asymmetrical nanowire whose both ends have mutually different diameters;

defining any one of a source region and a drain region by introducing impurities at an end of the nanowire;

forming a gate insulation film so as to enclose a part of the nanowire;

forming a gate electrode so as to enclose the gate insulation film; and

defining the remaining one of the source region and the drain region by introducing the impurities at the other end of the nanowire.

11. The method for manufacturing the nanowire field-effect transistor according to claim 10, wherein the asymmetrical nanowire is formed in a top-down method or a bottom-up method.

12. The method for manufacturing the nanowire field-effect transistor according to claim 10, wherein concentration of the impurities introduced to the end of the nanowire and concentration of the impurities introduced to the other end thereof are made different from each other.

13. The method for manufacturing the nanowire field-effect transistor according to claim 10, wherein concentration of the introduced impurities is 10¹⁷ cm⁻

3 to 10²¹ cm<sup>−

3</sup>.