Systems and methods for producing flat surfaces in interconnect structures

• US 9,123,703 B2
• Filed: 03/06/2014
• Issued: 09/01/2015
• Est. Priority Date: 06/24/2011
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Uzoh, Cyprian, Oganesian, Vage, Mohammed, Iiyas
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): BACHNER, ROBERT G
• Application Number:
  US14/199,181
• Publication Number:
  US 20140210102A1
• Time in Patent Office: 544 Days
• Field of Search: 257/774.E, 257/23.067 E, 257/21.584, 438/642, 438/643, 438/618, 438/597, 438/626, 438/629, 438/627, 438/692.E, 438/21.583
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32125 by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/7688 by deposition over sacrificial masking layer, e.g. lift-off lift-off per se H01L21/0272
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a co-planar or flat top surface. Another feature is a method of forming an interconnect structure that results in the interconnect structure having a surface that is angled upwards greater than zero with respect to a top surface of the substrate. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Claims

1. An intermediate workpiece obtained in fabrication of an apparatus comprising one or more semiconductor devices, the workpiece comprising:

a substrate comprising a plurality of holes in a top surface of the substrate, the holes being spaced from each other;

a conductive layer covering the substrate and extending into each said hole to provide in each said hole at least a part of an interconnect structure in the apparatus, wherein in the apparatus the part of the interconnect structure in each said hole is not connected by the conductive layer to any part of the interconnect structure in any other hole, the conductive layer being a pre-selected material whose entire bottom surface is in physical contact with one or more materials other than the pre-selected material, a top surface of the conductive layer having a recess over each said hole;

a sacrificial layer covering part of the conductive layer, the sacrificial layer being a first material different than the pre-selected material;

a separation layer covering the substrate and separating the conductive layer from the substrate, the separation layer being a material different than the first material;

wherein the entire sacrificial layer is higher than the entire separation layer; and

wherein a top surface of the workpiece consists of a top surface of the sacrificial layer and the top surface of the conductive layer not covered by the sacrificial layer.

2. The workpiece of claim 1 wherein the sacrificial layer is conformal.

3. The workpiece of claim 1 wherein the sacrificial layer is conductive.

4. The workpiece of claim 1 wherein the material of the separation layer is different from any material in a top surface of the substrate.

5. The workpiece of claim 1 wherein the separation layer is conductive.

6. The workpiece of claim 1 wherein the separation layer is a barrier layer.

7. The workpiece of claim 1 wherein the separation layer is an adhesion layer.

8. The workpiece of claim 1 wherein the separation layer is a coupling layer.

9. The workpiece of claim 1 wherein at least one said hole is a through-hole.

10. The workpiece of claim 9 wherein a part of the conductive layer in said through-hole comprises a through-silicon via.

11. The workpiece of claim 1 wherein each said hole is a cavity not passing through the substrate.

12. The workpiece of claim 1 wherein at least a part of the interconnect structure in at least one said cavity is a damascene structure.

13. An intermediate workpiece obtained in fabrication of an apparatus comprising one or more semiconductor devices, the workpiece comprising:

a substrate comprising a plurality of holes in a top surface of the substrate, the holes being spaced from each other;

a conductive layer covering the substrate and extending into each said hole to provide in each said hole at least a part of an interconnect structure in the apparatus, wherein in the apparatus the part of the interconnect structure in each said hole is not connected by the conductive layer to any part of the interconnect structure in any other hole, the conductive layer being a pre-selected material whose entire bottom surface is in physical contact with one or more materials other than the pre-selected material, the conductive layer having a recess over each said hole; and

a sacrificial layer covering part of the conductive layer, the sacrificial layer being a first material different than the pre-selected material;

wherein the entire sacrificial layer is higher than the entire bottom surface of the conductive layer; and

wherein a top surface of the workpiece consists of a top surface of the sacrificial layer and a top surface of the conductive layer not covered by the sacrificial layer.

14. The workpiece of claim 13 wherein the sacrificial layer is conformal.

15. The workpiece of claim 13 wherein the sacrificial layer is conductive.

16. The workpiece of claim 13 wherein the workpiece further comprises a separation layer covering the substrate and separating the conductive layer from the substrate, the separation layer being a material different than the first material.

17. The workpiece of claim 16 wherein the material of the separation layer is different from any material in a top surface of the substrate.

18. The workpiece of claim 16 wherein the separation layer is conductive.

19. The workpiece of claim 16 wherein the separation layer is a barrier layer.

20. The workpiece of claim 16 wherein the separation layer is an adhesion layer.

21. The workpiece of claim 16 wherein the separation layer is a coupling layer.

22. The workpiece of claim 13 wherein at least one said hole is a through-hole.

23. The workpiece of claim 22 wherein a part of the conductive layer in said through-hole comprises a through-silicon via.

24. The workpiece of claim 13 wherein each said hole is a cavity not passing through the substrate.

25. The workpiece of claim 13 wherein at least a part of the interconnect structure in at least one said cavity is a damascene structure.