Method for bonding two silicon substrates, and a correspondeing system of two silicon substrates

• US 9,123,716 B2
• Filed: 12/19/2012
• Issued: 09/01/2015
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Gonska, Julian, Weber, Heribert, Frey, Jens, Schary, Timo, Mayer, Thomas
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US13/719,799
• Publication Number:
  US 20130161820A1
• Time in Patent Office: 986 Days
• Field of Search: 438/107, 438/687, 438/630, 438/642, 438/688, 257/771, 257/770, 257/776
• US Class Current: 1/1
• CPC Class Codes: B81B 2201/0235 Accelerometers
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: H01L 21/185 Joining of semiconductor bodies for junction formation
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 23/488 consisting of soldered or bonded constructions bump connectors H01L24/01
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/0132 Binary Alloys
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/16251 Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Abstract

A method for bonding two silicon substrates and a corresponding system of two silicon substrates. The method includes: providing first and second silicon substrates; depositing a first bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1 and 5% on a first bonding surface of the first silicon substrate; depositing a second bonding layer of germanium above the first bonding surface or above a second bonding surface of the second silicon substrate; subsequently joining the first and second silicon substrates, so that the first and the second bonding surfaces lie opposite each other; and implementing a thermal treatment step to form an eutectic bonding layer of aluminum-germanium or containing aluminum-germanium as the main component, between the first silicon substrate and the second silicon substrate, spikes which contain aluminum as a minimum and extend into the first silicon substrate, forming at least on the first bonding surface.

Claims

1. A method for bonding two silicon substrates, the method comprising:

providing a first silicon substrate and a second silicon substrate;

depositing a first bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1% and 5% on a first bonding surface of the first silicon substrate;

depositing a second bonding layer of germanium above the first bonding surface or above a second bonding surface of the second silicon substrate;

subsequently bonding the first silicon substrate and the second silicon substrate, so that the first bonding surface and the second bonding surface lie opposite each other; and

implementing a thermal treatment step to form a eutectic bonding layer of aluminum-germanium or containing aluminum-germanium as main component, between the first silicon substrate and the second silicon substrate, spikes, which contain aluminum as a minimum and extend into the first silicon substrate, forming at least on the first bonding surface.

2. The method of claim 1, further comprising:

depositing, prior to depositing the second bonding layer of germanium, a third bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1% and 5% on the second bonding surface of the second silicon substrate, spikes, which contain aluminum as a minimum and extend into the second silicon substrate, forming on the second bonding surface during the thermal treatment.

3. The method of claim 2, further comprising:

depositing, prior to the bonding, a fourth bonding layer of germanium or of aluminum-silicon-copper having a silicon component between 0.1% and 5% above the first bonding surface.

4. The method of claim 1, further comprising:

depositing, prior to the bonding, a fifth bonding layer of aluminum-silicon-copper having a silicon component between 0.1 and 5% above the second bonding surface.

5. The method of claim 2, further comprising:

depositing, prior to the bonding, a sixth bonding layer of pure aluminum or of aluminum-copper having a copper component between 0.1% and 5% above at least one of the first bonding surface and the second bonding surface.

6. The method of claim 1, wherein the thermal treatment is performed within a temperature range between 400°

C. and 550°

C.

7. The method of claim 1, wherein the copper component is between 0.5% and 1%.

8. The method of claim 3, wherein the silicon component is between 1% and 2%.

14. The method of claim 1, wherein the thermal treatment is performed within a temperature range between 425°

C. and 500°

C.

9. A system of two silicon substrates, comprising:

a first silicon substrate;

a second silicon substrate; and

a eutectic bonding layer made of aluminum-germanium or having aluminum-germanium as main component of aluminum-germanium, between the first silicon substrate and the second silicon substrate, spikes, which contain aluminum as a minimum and extend into the first silicon substrate, forming at least on the first bonding surface.

10. The system of claim 9, wherein spikes which contain aluminum as a minimum and which extend into the second silicon substrate form on the second bonding surface.

11. The system of claim 9, wherein the first silicon substrate is a wafer substrate, and the second silicon substrate is a sensor-wafer substrate.

12. The system of claim 9, wherein the eutectic bonding layer has at least one of a copper component between 0.1% and 5%, and a silicon component between 0.1% and 5%.

13. The system of claim 11, wherein the first silicon substrate is a wafer substrate, which is a cap-wafer substrate, and the second silicon substrate is a sensor-wafer substrate.