Accurate and cost efficient linear hall sensor with digital output
First Claim
1. A circuit, comprising:
- a chopping generation circuit configured to receive an analog signal and to periodically switch a polarity of the analog signal to generate a chopped signal having different polarities in temporally adjacent chopping phases;
an analog-to-digital converter (ADC) configured to convert the chopped signal to a digital signal;
a digital signal processing unit comprising a delay removal circuitry configured to generate a first and second digital signal components from a same chopping phase of the digital signal, and a logic element configured to add or subtract the first and second digital signal components from the same chopping phase to generate an offset compensated digital output signal;
a first signal path configured to provide the digital signal from the ADC to the logic element as the first digital signal component; and
a second signal path having one or more delay removal elements configured to operate upon the digital signal to generate the second digital signal component, which is provided to the logic element.
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Accused Products
Abstract
One embodiment of the present invention relates to a magnetic sensor circuit having a magnetic field sensor device configured to generate a digital signal proportional to an applied magnetic field. An analog-to-digital converter converts the analog signal to a digital signal that is provided to a digital signal processing unit, which is configured to digitally track the analog output signal. The digital tracking unit comprises a delay removal circuitry configured to generate a plurality of digital signal component corresponding to a chopping phase. A non-delayed offset compensated digital output signal may be generated within the chopping phase by mathematically operating upon (e.g., adding or subtracting) the plurality of digital signal components, generated by the delay removal circuitry.
24 Citations
18 Claims
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1. A circuit, comprising:
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a chopping generation circuit configured to receive an analog signal and to periodically switch a polarity of the analog signal to generate a chopped signal having different polarities in temporally adjacent chopping phases; an analog-to-digital converter (ADC) configured to convert the chopped signal to a digital signal; a digital signal processing unit comprising a delay removal circuitry configured to generate a first and second digital signal components from a same chopping phase of the digital signal, and a logic element configured to add or subtract the first and second digital signal components from the same chopping phase to generate an offset compensated digital output signal; a first signal path configured to provide the digital signal from the ADC to the logic element as the first digital signal component; and a second signal path having one or more delay removal elements configured to operate upon the digital signal to generate the second digital signal component, which is provided to the logic element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for digitally tracking an analog signal, comprising:
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generating an analog signal; periodically switching a polarity of the analog signal to generate a chopped signal having different polarities in temporally adjacent chopping phases; generating a tracked digital signal that tracks the chopped signal; generating a first digital signal component from the tracked digital signal over a plurality of chopping phases, which has a value that is clamped for one or more clock periods of a first one of the plurality of chopping phases; generating a second digital signal component from the tracked digital signal over a plurality of chopping phases, which has a value that is clamped for one or more clock periods of a second one of the plurality of chopping phases immediately subsequent to the first one of the plurality of chopping phases; providing the first digital signal component to a first register within a first signal path that that is configured to store the first digital signal component, and providing the second digital signal component to a second register within a second signal path that is configured to store the second digital signal component; and mathematically operating upon the first and second digital signal components to generate an offset compensated digital output signal. - View Dependent Claims (11, 12, 13)
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14. A circuit, comprising:
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a chopping generation circuit configured to receive an analog signal and to periodically switch a polarity of the analog signal to generate a chopped signal having different polarities in temporally adjacent chopping phases; and an analog-to-digital converter (ADC) configured to convert the chopped signal to a digital signal; and a digital tracking unit having an input coupled to an output of the chopping generation circuit and comprising; a first signal path connected to the input and configured to provide a first digital signal component corresponding to a first chopping phase to a first input of a logic element; a second signal path comprising a low-pass filtering element connected to the input, wherein the low-pass filtering element is configured to average signals from a plurality of chopping phases and to provide the averaged signals to a second input of the logic element as a second digital signal component; wherein the logic element is configured to superimpose the second digital signal component from the first digital signal component to generate a non-delayed digital output signal. - View Dependent Claims (15, 16, 17, 18)
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Specification