Clock and data recovery for NFC transceivers
First Claim
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1. A circuit comprising a phase-locked loop configured to recover a clock from a received input signal in a first mode and the phase-locked loop further configured for oversampling of an output signal in a second, different mode, the phase-locked further configured to detect an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples.
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Abstract
Exemplary embodiments are directed to data and clock recovery in NFC transceivers. A transceiver may include a phase-locked loop configured to recover a clock from a received input signal in a first mode and enable for oversampling of an output signal in a second, different mode.
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Citations
23 Claims
- 1. A circuit comprising a phase-locked loop configured to recover a clock from a received input signal in a first mode and the phase-locked loop further configured for oversampling of an output signal in a second, different mode, the phase-locked further configured to detect an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples.
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8. A circuit, comprising:
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a frequency-phase detector; and an amplitude-shift keying detection circuit coupled to the frequency-phase detector and configured to detect an amplitude-shift keying mode wherein a signal undergoes 100% amplitude-shift keying of lacking a transition of the signal over a plurality of samples. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A method, comprising:
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recovering a clock from a received input signal with a phase-locked loop in a first near-field communication (NFC) mode; detecting an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples; and oversampling of an output signal with the phase-locked loop in a second, different NFC mode, the recovering comprising utilizing a first circuit path of the phase-locked loop and the oversampling comprising utilizing a second, different circuit path of the phase-locked loop. - View Dependent Claims (15, 16)
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17. A method, comprising:
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receiving an input signal at a phase-frequency detector in a tag mode; and detecting an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples while receiving the input signal in the tag mode. - View Dependent Claims (18, 19, 20, 21)
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22. A device, comprising:
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means for recovering a clock from a received input signal in a first NFC mode, the means for recovering utilizing a first circuit path of a phase-locked loop means; means for detecting an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples; and means for oversampling of an output signal in a second, different near-field communication (NFC) mode, the means for oversampling utilizing a second, different circuit path in a phase-locked loop means.
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23. A device, comprising:
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means for receiving an input signal in a tag mode; and means for detecting an amplitude-shift keying mode wherein the input signal undergoes 100% amplitude-shift keying of lacking a transition of the input signal over a plurality of samples while receiving the input signal in the tag mode.
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Specification