Semiconductor device and driving method thereof

• US 9,129,667 B2
• Filed: 05/22/2013
• Issued: 09/08/2015
• Est. Priority Date: 05/25/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takahashi, Yasuyuki, Yoneda, Seiichi
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): HUERTA, PABLO S
• Application Number:
  US13/900,140
• Publication Number:
  US 20130315011A1
• Time in Patent Office: 839 Days
• Field of Search: 365/189.011
• US Class Current: 1/1
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor device in which a nonvolatile memory can normally operate and power saving can be performed with a P-state function, and a driving method of the semiconductor device are provided. The semiconductor device includes: a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core; a first memory circuit and a second memory circuit which store state data; a second circuit generating a power supply voltage and a third circuit generating a clock which are electrically connected to the first circuit; and the processor core electrically connected to the second circuit and the third circuit through a switch. The processor cores includes: a volatile memory; and a nonvolatile memory transmitting and receiving data to/from the first memory.

Claims

1. A semiconductor device comprising:

a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core;

a first memory circuit and a second memory circuit which store state data;

a second circuit generating a power supply voltage and a third circuit generating a clock, the second circuit and the third circuit being electrically connected to the first circuit; and

the processor core electrically connected to the second circuit and the third circuit through a switch,

wherein the processor cores comprises;

a first memory; and

a second memory transmitting and receiving data to/from the first memory; and

wherein the first circuit reads state data stored in the first memory circuit and determines whether data in processing in the processor core is stored with a current state data when the first circuit receives an instruction for an off operation.

2. The semiconductor device according to claim 1, wherein state data including a driving voltage and a clock frequency supplied to the processor core is stored in the first memory circuit.

3. The semiconductor device according to claim 1, wherein state data including a driving voltage and a clock frequency supplied to the processor core before the first circuit receives an instruction for an off operation is stored in the second memory circuit.

4. The semiconductor device according to claim 1, wherein the first circuit, the switch, and the processor core are electrically connected to a power gating circuit.

5. The semiconductor device according to claim 1, comprising a plurality of the processor cores, a plurality of the first circuits, a plurality of the second circuits, and a plurality of the switches.

6. The semiconductor device according to claim 1, wherein the second memory comprises a transistor in which a channel formation region includes an oxide semiconductor.

7. A driving method of a semiconductor device, comprising the steps of:

operating a processor core with a first state;

performing an off operation; and

performing an on operation,

wherein the off operation comprises the steps of;

keeping the first state or changing the first state into a second state;

reading data from a first memory in the processor core;

writing the data to a second memory in the processor core; and

turning off the processor core, and

wherein the on operation comprises the steps of;

keeping a state in the off operation or changing the state in the off operation into a third state;

turning on the processor core;

reading the data from the second memory;

writing the data to the first memory; and

changing the state in the off operation or the third state into the first state.

8. The driving method of the semiconductor device, according to claim 7, wherein the off operation further comprises the step of determining whether the first state is kept or is changed into the second state.

9. The driving method of the semiconductor device, according to claim 7, wherein the on operation further comprising the step of determining whether the state in the off operation is kept or changed into the third state.

10. The driving method of the semiconductor device, according to claim 7, wherein the first state includes a driving voltage and a clock frequency supplied during an operation of the processor core before an instruction for the off operation is given.

11. The driving method of the semiconductor device, according to claim 7, wherein the second state includes a driving voltage and a clock frequency at which the data is normally written to the second memory in the processor core.

12. The driving method of the semiconductor device, according to claim 7, wherein the third state includes a driving voltage and a clock frequency at which the data is normally read from the second memory in the processor core.

13. A driving method of a semiconductor device, comprising the steps of:

storing first state data including a driving voltage and a clock frequency supplied to a processor core in a first memory device;

performing an off operation; and

performing an on operation,

wherein, in the off operation, a first circuit configured to control a state receives an instruction for the off operation, the first state data is stored in a second memory device, the first state data stored in the first memory device is rewritten into second state data, the driving voltage and the clock frequency of the processor core are changed in accordance with the second state data, the first circuit requests an instruction for the off operation from a power gating circuit, data stored in a first memory in the processor core is read, the data is written to a second memory in the processor core, and electrical connection between the processor core and each of a second circuit generating a power supply voltage and a third circuit generating a clock is broken.

14. The driving method of the semiconductor device, according to claim 13, wherein, in the on operation, the first circuit receives an instruction for the on operation, the second state data stored in the first memory device is rewritten into third state data, the driving voltage and the clock frequency of the processor core are changed in accordance with the third state data, the first circuit requests an instruction for the on operation from the power gating circuit, the processor core and each of the second circuit and the third circuit are reconnected, the data stored in the second memory is read, the data is written to the first memory, the third state data stored in the first memory device is rewritten into the first state data stored in the second memory device, and the driving voltage and the clock frequency of the processor core are changed in accordance with the first state data.

15. The driving method of the semiconductor device, according to claim 13,

wherein, in the on operation, the first circuit receives an instruction for the on operation, and the first circuit reads the first state data or the second state data stored in the first memory device and determines whether the data is normally read from the second memory in the processor core with the first state data or the second state data,

wherein, when the data is normally read from the second memory, the first circuit requests an instruction for the on operation from the power gating circuit, the processor core and each of the second circuit and the third circuit are reconnected, the data stored in the second memory is read, the data is written to the first memory, the state data stored in the first memory device is rewritten into the first state data stored in the second memory device, and the driving voltage and the clock frequency of the processor core are changed in accordance with the first state data, and

wherein, when the data is not normally read from the second memory, the first state data or the second state data stored in the first memory device is rewritten into third state data, the driving voltage and the clock frequency of the processor core are changed in accordance with the third state data, the first circuit requests the instruction for the on operation from the power gating circuit, the processor core and each of the second circuit and the third circuit are reconnected, the data stored in the second memory is read, the data is written to the first memory, the state data stored in the first memory device is rewritten into the first state data stored in the second memory device, and the driving voltage and the clock frequency of the processor core are changed in accordance with the first state data.

16. The driving method of the semiconductor device, according to claim 13, wherein the third state data includes data on a driving voltage and a clock frequency at which the data is normally read from the second memory in the processor core.

17. The driving method of the semiconductor device, according to claim 13, wherein, in the on operation, the first circuit receives an instruction for the on operation, the first circuit requests an instruction for the on operation from the power gating circuit, the processor core and each of the second circuit and the third circuit are reconnected, the data stored in the second memory is read, the data is written to the first memory, the state data stored in the first memory device is rewritten into the first state data stored in the second memory device, and the driving voltage and the clock frequency of the processor core are changed in accordance with the first state data.

18. The driving method of the semiconductor device, according to claim 13, wherein the first state data includes data on a driving voltage and a clock frequency supplied during an operation of the processor core before the first circuit receives the instruction for the off operation.

19. The driving method of the semiconductor device, according to claim 13, wherein the second state data includes data on a driving voltage and a clock frequency at which the data is normally written to the second memory in the processor core.

20. The driving method of the semiconductor device, according to claim 13, wherein, in the off operation or the on operation, the processor core is selected.