Semiconductor device identifier generation method and semiconductor device
First Claim
1. A method of generating an identifier from a semiconductor device comprising a volatile memory having a plurality of memory cells, the method comprising:
- (a) causing the memory cells to assume a first plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells;
(b) retrieving, by a processor circuit, the pseudo-random bit values from at least a subset of the plurality of memory cells;
(c) causing the memory cells to assume at least a second plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; and
(d) generating the identifier by averaging at least some of the first plurality pseudo-random bit values and the at least second plurality of pseudo-random bit values.
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Abstract
A method (100) is disclosed of generating an identifier from a semiconductor device (600) comprising a volatile memory (610) having a plurality of memory cells. The method comprises causing (110) the memory cells to assume a plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; retrieving (120) the bit values from at least a subset of the plurality of memory cells; and generating the identifier from the retrieved bit values. The method (100) is based on the realization that a substantial amount of the cells of a volatile memory can assume a bit value that is governed by underlying variations in manufacturing process parameters; this for instance occurs at power-up for an SRAM or after a time period without refresh for a DRAM. This can be used for several identification purposes, such as identifying a semiconductor device (600) comprising the volatile memory (610), or for secure key generation by mapping error-correcting code words onto the identifier bit locations. The present invention further includes a semiconductor device (600, 1000) configured to be subjectable to the method (100) of the present invention.
20 Citations
37 Claims
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1. A method of generating an identifier from a semiconductor device comprising a volatile memory having a plurality of memory cells, the method comprising:
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(a) causing the memory cells to assume a first plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; (b) retrieving, by a processor circuit, the pseudo-random bit values from at least a subset of the plurality of memory cells; (c) causing the memory cells to assume at least a second plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; and (d) generating the identifier by averaging at least some of the first plurality pseudo-random bit values and the at least second plurality of pseudo-random bit values. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A method of generating an identifier from a semiconductor device comprising a volatile memory having a plurality of memory cells, the method comprising:
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(a) causing the memory cells to assume a first plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; (b) retrieving, by a processor circuit, the pseudo-random bit values from at least a subset of the plurality of memory cells; (c) causing the memory cells to assume at least a second plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; and (d) generating the identifier by averaging at least some of the first plurality pseudo-random bit values and the at least second plurality of pseudo-random bit values, wherein the semiconductor device further comprises; functionality requiring a key comprising a plurality of information symbols for its operation; and a mapping function for mapping the bit values of one or more code words from a family of code words onto respective bit values of the identifier, each code word comprising a further plurality of information symbols; the method further comprising; retrieving the one or more code words from the identifier with the mapping function; error-correcting the one or more retrieved code words; creating the key from the information symbols of the one or more error-corrected code words; and operating the functionality using the key. - View Dependent Claims (21, 22, 23, 24)
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25. A semiconductor device comprising:
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a volatile memory having a plurality of memory cells; and a memory controller configured to cause the plurality of memory cells to assume a plurality of pseudo-random bit values that are responsive to variations in the microstructure of the memory cells by storing a predefined set of pseudo-random bit values in the plurality memory cells, and allowing at least one of the plurality of memory cells to lose their predefined value based upon a charge leakage rate of the memory cells; and retrieve, from at least a subset of the plurality of memory cells in response to losing their predefined value, an identifier including the respective pseudo-random bit values. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34, 35)
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36. A method of generating an identifier from a semiconductor device including a volatile memory having a plurality of memory cells, the method comprising:
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storing a first predefined set of bit values in the memory cells by powering-up the memory cells using a first power-up voltage; causing at least one of the plurality of memory cells to lose the first predefined bit value according to a pseudo-random parameter that includes charge leakage rate of the memory cells; retrieving, by a processor circuit, the first predefined bit values from at least a subset of the plurality of memory cells thereby creating a first set of retrieved bit values; storing a second predefined set of bit values in the memory cells by powering-up the memory cells using a second power-up voltage that is different from the first power-up voltage; causing at least one of the plurality of memory cells to lose the second predefined bit value according to the pseudo-random parameter that includes charge leakage rate of the memory cells; retrieving the second predefined bit values from at least a subset of the plurality of memory cells thereby creating a second set of retrieved bit values; and generating the identifier by combining the first set of retrieved bit values and the second set of retrieved bit values. - View Dependent Claims (37)
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Specification