High voltage field balance metal oxide field effect transistor (FBM)
First Claim
1. A semiconductor device, comprising:
- a semiconductor substrate of a first conductivity type;
an epitaxial layer of the first conductivity type disposed on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped;
a body region of a second conductivity type that is opposite of the first conductivity type, a source region of the first conductivity type and a gate disposed near the top surface of the surface shielded region and a drain disposed at a bottom surface of the semiconductor substrate;
a plurality of trenches formed in the surface shielded region, wherein the trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material configured to be in electrical contact with a source electrode on top of the surface shielded region and in electrical contact with the source region;
a plurality of buried doped regions of the second conductivity type, wherein each is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region; and
one or more charge linking paths of the second conductivity type positioned along one or more trench walls of the plurality of trenches and configured to electrically connect a buried doped region to the body region.
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Accused Products
Abstract
A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
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Citations
12 Claims
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1. A semiconductor device, comprising:
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a semiconductor substrate of a first conductivity type; an epitaxial layer of the first conductivity type disposed on a top surface of the semiconductor substrate, wherein the epitaxial layer includes a surface shielded region that is heavily doped positioned above a voltage blocking region that is lightly doped; a body region of a second conductivity type that is opposite of the first conductivity type, a source region of the first conductivity type and a gate disposed near the top surface of the surface shielded region and a drain disposed at a bottom surface of the semiconductor substrate; a plurality of trenches formed in the surface shielded region, wherein the trenches are lined with a trench insulation material and filled with an electrically conductive trench filling material configured to be in electrical contact with a source electrode on top of the surface shielded region and in electrical contact with the source region; a plurality of buried doped regions of the second conductivity type, wherein each is positioned below one of the plurality of trenches, and wherein the buried doped regions extend to a depth substantially the same as the bottom surface of the surface shielded region; and one or more charge linking paths of the second conductivity type positioned along one or more trench walls of the plurality of trenches and configured to electrically connect a buried doped region to the body region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification