Silicon and silicon germanium nanowire structures

• US 9,129,829 B2
• Filed: 05/09/2014
• Issued: 09/08/2015
• Est. Priority Date: 12/01/2010
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Intel Corporation
• Inventors: Kuhn, Kelin J., Kim, Seiyon, Rios, Rafael, Cea, Stephen M., Giles, Martin D., Cappellani, Annalisa, Rakshit, Titash, Chang, Peter, Rachmady, Willy
• Primary Examiner(s): ZHU, SHENG-BAI
• Application Number:
  US14/274,592
• Publication Number:
  US 20140326952A1
• Time in Patent Office: 487 Days
• Field of Search: 257/9, 257/24, 257/401, 257/E21.218, 257/E21.409, 257/E21.561, 257/E29.168, 438/283, 438/198
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 : having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Claims

1. A method of forming a nanowire device comprising:

forming alternating layers of an epitaxial silicon material on epitaxial silicon germanium material on a substrate;

forming fin structures by etching the alternating layers and forming trenches adjacent to the fin structures;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate;

filling a gap in the spacers that is adjacent to the fin structures with a second spacer;

forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers;

removing one of the silicon and the epitaxial silicon germanium layers from the fin structures disposed between the spacers.

2. The method of claim 1 wherein the second spacer material comprises at least one of a spacer like material and a low-k material.

3. The method of claim 1 further comprising wherein the gap in the spacers is filled on a source/drain side of the spacer.

4. The method of claim 1 further comprising wherein the gap in the spacers is filled on a gate side of the spacer.

5. A method of forming a nanowire device comprising:

forming alternating layers of an epitaxial silicon material on epitaxial silicon germanium material on a (100) substrate comprising a <

111>

channel;

forming fin structures by etching the alternating layers and forming trenches adjacent to the fin structures;

forming spacers across and on the fin structures;

removing a portion of the fin structures from source/drain regions on the substrate, and then forming source/drain structures on the source/drain regions, wherein the source/drain regions are adjacent the spacers;

removing the epitaxial silicon layers from the fin structures disposed between the spacers by using a wet etch that is selective to silicon and not to silicon germanium.

6. The method of claim 5 wherein silicon germanium nanowires are partially etched after removing all of the silicon between the SiGe nanowires of the fin structure.

7. The method of claim 6 wherein the wet etch comprises an anisotropic etch to minimize lateral etching within the spacers.

8. A method of forming a nanowire device comprising:

patterning alternating layers of nitride and oxide disposed on a silicon substrate to expose a back region and a trench region;

forming one of a silicon material and a silicon germanium material in the trench and back regions;

forming a hard mask on one of the silicon germanium and silicon;

forming a fin structure by removing a portion of the alternating layers of nitride and oxide not covered by the hard mask; and

forming nanowire structures by oxidizing the fin structure and then removing the oxidized portions.

9. The method of claim 8 further comprising wherein the nanowire structures are disposed across substantially all of the device.

10. A method of forming a nanowire device comprising:

patterning alternating layers of nitride and oxide disposed on a silicon substrate to expose a back region and a trench region;

forming one of a silicon material and a silicon germanium material in the trench and back regions;

forming a hard mask on one of the silicon germanium and silicon;

forming a forming a fin structure by removing a portion of the alternating layers of nitride and oxide not covered by the hard mask;

forming a second hard mask around the fin structure;

forming a gate region adjacent the fin structure, wherein a portion of the fin structure may be exposed;

forming nanowire structures by oxidizing the fin structure and then removing the oxidized portions.

11. The method of claim 10 further comprising wherein the nanowire structures are disposed only in the gate area.

12. The method of claim 10 further comprising wherein the oxidized portions of the fin structure is removed by:

etching the oxide with a wet etch; and

etching one of the silicon and silicon germanium with an anisotropic etch.

13. A method of forming a semiconductor device, the method comprising:

forming an epitaxial silicon germanium (SiGe) layer on a bulk crystalline silicon substrate;

forming an epitaxial silicon layer on the epitaxial SiGe layer;

forming a fin structure from the epitaxial SiGe layer and the epitaxial silicon layer;

forming a sacrificial gate electrode over the fin structure, defining a pair of source/drain regions of the fin structure;

forming dielectric spacers adjacent to sidewalls of the sacrificial gate electrode and over the fin structure;

removing portions of both the epitaxial silicon layer and the epitaxial SiGe layer from the pair of source/drain regions;

forming epitaxial silicon source/drain regions for the fin structure, the epitaxial silicon source/drain regions adjacent to the dielectric spacers;

removing the sacrificial gate electrode from between the dielectric spacers to expose a portion of the fin structure between the dielectric spacers;

removing the epitaxial SiGe layer from the portion of the fin structure between the dielectric spacers to form an epitaxial silicon nanowire in the portion of the fin structure between the dielectric spacers;

forming a high-k gate dielectric layer on the epitaxial silicon nanowire; and

forming a metal gate electrode on the high-k gate dielectric layer, the metal gate electrode around the epitaxial silicon nanowire.