Transistor structures and integrated circuitry comprising an array of transistor structures

• US 9,129,847 B2
• Filed: 09/20/2013
• Issued: 09/08/2015
• Est. Priority Date: 07/17/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando
• Primary Examiner(s): Jahan, Bilkis
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US14/032,541
• Publication Number:
  US 20140021550A1
• Time in Patent Office: 718 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.

Claims

1. A transistor structure, comprising:

a pair of spaced source/drain regions within semiconductive material;

an electrically floating body region within the semiconductive material;

the floating body region having a base, an insulative material being against the base, conductively doped semiconductive material being against the insulative material beneath the base;

a first gate spaced apart from and capacitively coupled to the body region between the source/drain regions; and

a pair of opposing conductively interconnected second gates spaced and electrically isolated from the first gate, the pair of second gates being laterally outward of the first gate, the second gates being spaced from and capacitively coupled to the body region laterally outward of the first gate and capacitively coupled to the body region between the pair of source/drain regions.

2. The structure of claim 1 wherein the pair of second gates is conductively interconnected by conductive material extending elevationally over the first gate between the pair of second gates.

3. The structure of claim 1 wherein the first gate is separated from the second gates by at least two insulative materials.

4. A transistor structure, comprising:

a substrate comprising an island of semiconductive material;

insulative material around and underneath the island and contacting semiconductive material of the island;

a pair of spaced source/drain regions within the island of semiconductive material;

an electrically floating body region within the island of semiconductive material;

a first gate spaced apart from and capacitively coupled to the island floating body region at least partially between the island source/drain regions; and

a pair of conductive second gates spaced from and laterally outward of the first gate, the second gates being spaced from and capacitively coupled to the island floating body region laterally outward of the first gate and at least partially between the pair of source/drain regions.

5. The structure of claim 4 comprising conductively doped semiconductive material around and underneath the island outwardly of the insulative material.

6. Integrated circuitry comprising an array of transistor structures, comprising:

a series of spaced islands of semiconductive material within a substrate; and

individual transistor structures associates with individual of the spaced islands, the individual transistor structures individually comprising;

a pair of source/drain regions within the semiconductive material of the respective island;

an electrically floating body region within the semiconductive material of the respective island;

a first gate comprised of a gate line which is common to and extends over the series of spaced islands at least partially between the respective pairs of source/drain regions, the first gate line having lateral sides and being spaced apart from and capacitively coupled to the respective body regions of the respective islands; and

a pair of opposing conductively interconnected second gates spaced from the first gate and being laterally outward of the gate line, the second gates being spaced from and capacitively coupled to the respective body regions laterally outward of the respective first gates and at least partially between the respective pairs of source/drain regions of the respective islands, the pairs of opposing interconnected second gates comprising a conductive line which is common to the series of spaced islands and extends above and to the lateral sides of the gate line.

7. The integrated circuitry of claim 6 comprising a first conductive contact connected to the gate line and a different second conductive contact connected to the conductive line.

8. The integrated circuitry of claim 6 wherein the gate line is longer in length than the conductive line.

9. The integrated circuitry of claim 6 comprising insulative material around and underneath the respective islands and contacting semiconductive material of the respective islands;

and

conductively doped semiconductive material around and underneath the respective islands outwardly of the insulative material.

10. The integrated circuitry of claim 6 wherein the conductive line has an end and the gate line has an end proximate the conductive line end, said gate line end and said conductive line end not being longitudinally co-located.

11. The integrated circuitry of claim 10 wherein the gate line is longer in length than the conductive line.

12. The integrated circuitry of claim 10 wherein the gate line end is longitudinally outward of the conductive line end.

13. The integrated circuitry of claim 12 wherein the gate line is longer in length than the conductive line.

14. A transistor structure, comprising:

a pair of spaced source/drain regions within semiconductive material;

an electrically floating body region within the semiconductive material;

a first gate spaced apart from and capacitively coupled to the body region between the source/drain regions;

a pair of opposing conductively interconnected second gates spaced and electrically isolated from the first gate, the pair of second gates being laterally outward of the first gate, the second gates being spaced from and capacitively coupled to the body region laterally outward of the first gate and capacitively coupled to the body region between the pair of source/drain regions, the second gates having respective laterally outermost edges, the second gates being conductively interconnected by conductive material extending elevationally over the first gate between the pair of second gates; and

gate dielectric material between the first gate and the body region and between the second gates and the body region, the gate dielectric material having opposing laterally outermost edges which are laterally co-located with those of the respective second gates.

15. Integrated circuitry comprising an array of transistor structures, comprising:

a series of individual transistor structures individually comprising;

a pair of source/drain regions within semiconductive material;

an electrically floating body region within the semiconductive material;

a first gate comprised of a gate line which is common to and extends over the semiconductive material of the series at least partially between the respective pairs of source/drain regions, the first gate line having lateral sides and being spaced apart from and capacitively coupled to the respective body regions; and

a pair of opposing conductively interconnected second gates spaced from the first gate and being laterally outward of the gate line, the second gates being spaced from and capacitively coupled to the respective body regions laterally outward of the respective first gates and at least partially between the respective pairs of source/drain regions, the pairs of opposing interconnected second gates comprising a conductive line which is common to the series and extends above and to the lateral sides of the gate line; and

the gate line being longer in length than the conductive line.

16. The integrated circuitry of claim 15 comprising insulative material underneath and contacting the semiconductive material;

and

conductively doped semiconductive material underneath and contacting the insulative material.

17. Integrated circuitry comprising an array of transistor structures, comprising:

a series of individual transistor structures individually comprising;

a pair of source/drain regions within semiconductive material;

an electrically floating body region within the semiconductive material;

a first gate comprised of a gate line which is common to and extends over the semiconductive material of the series at least partially between the respective pairs of source/drain regions, the first gate line having lateral sides and being spaced apart from and capacitively coupled to the respective body regions; and

a pair of opposing conductively interconnected second gates spaced from the first gate and being laterally outward of the gate line, the second gates being spaced from and capacitively coupled to the respective body regions laterally outward of the respective first gates and at least partially between the respective pairs of source/drain regions, the pairs of opposing interconnected second gates comprising a conductive line which is common to the series and extends above and to the lateral sides of the gate line; and

the conductive line having an end and the gate line having an end proximate the conductive line end, said gate line end and said conductive line end not being longitudinally co-located.

18. The integrated circuitry of claim 17 wherein the gate line is longer in length than the conductive line.

19. The integrated circuitry of claim 17 comprising insulative material underneath and contacting the semiconductive material;

and

conductively doped semiconductive material underneath and contacting the insulative material.

20. The integrated circuitry of claim 17 wherein the gate line end is longitudinally outward of the conductive line end.

21. The integrated circuitry of claim 20 wherein the gate line is longer in length than the conductive line.

22. A transistor structure, comprising:

a pair of spaced source/drain regions within semiconductive material;

an electrically floating body region within the semiconductive material;

a first gate spaced apart from and capacitively coupled to the body region between the source/drain regions;

a pair of opposing conductively interconnected second gates spaced and electrically isolated from the first gate, the pair of second gates being laterally outward of the first gate, the second gates being spaced from and capacitively coupled to the body region laterally outward of the first gate and capacitively coupled to the body region between the pair of source/drain regions, the second gates having respective laterally outermost edges, the second gates individually comprising an arcuate laterally outer surface that joins with its respective laterally outermost edge; and

gate dielectric material between the first gate and the body region and between the second gates and the body region, the gate dielectric material having opposing laterally outermost edges which are laterally co-located with those of the respective second gates.

23. The structure of claim 22 wherein the pair of second gates is conductively interconnected by conductive material extending elevationally over the first gate between the pair of second gates.