Method for efficiently fabricating memory cells with logic FETs and related structure

• US 9,129,856 B2
• Filed: 07/08/2011
• Issued: 09/08/2015
• Est. Priority Date: 07/08/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Xia, Wei, Chen, Xiangdong
• Primary Examiner(s): Sun, Yu-Hsi D
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US13/179,248
• Publication Number:
  US 20130009231A1
• Time in Patent Office: 1,523 Days
• Field of Search: 257/316, 257/368, 257/E21.616, 257/E27.06
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

According to one exemplary embodiment, a method for concurrently fabricating a memory region with a logic region in a common substrate includes forming a lower dielectric segment in the common substrate in the memory and logic regions. The method also includes forming a polysilicon segment over the lower dielectric segment in the memory region, while concurrently forming a sacrificial polysilicon segment over the lower dielectric segment in the logic region. Furthermore, the method includes removing from the logic region the lower dielectric segment and the sacrificial polysilicon segment. The method additionally includes forming a high-k segment in the logic region over the common substrate, and in the memory region over the polysilicon segment and forming a metal segment over the high-k segment in the logic and memory regions. An exemplary structure achieved by the described exemplary method is also disclosed.

Claims

1. A method for concurrently fabricating a memory region with a logic region on a common substrate, said method comprising:

forming a lower dielectric segment in each of said memory and logic regions over said common substrate in a stacking direction;

forming a polysilicon layer over said lower dielectric segment in said stacking direction in each of said memory and logic regions;

etching said polysilicon layer to form a polysilicon segment in said memory region and a sacrificial polysilicon segment in said logic region;

forming a first spacer in said logic region and a second spacer in said memory region, said first spacer being adjacent to said sacrificial polysilicon segment in a first direction that is perpendicular to said stacking direction, and said second spacer being adjacent to said polysilicon segment in said first direction;

removing said lower dielectric segment and said sacrificial polysilicon segment from said logic region;

forming a first high-k segment in said logic region over said common substrate in said stacking direction and adjacent to said first spacer in said first direction;

forming a second high-k segment in said memory region over said polysilicon segment in said stacking direction and adjacent to said second spacer in said first direction;

forming a first metal segment over said first high-k segment in said logic region in said stacking direction; and

forming a second metal segment over said second high-k segment in said memory region in said stacking direction.

2. The method of claim 1, wherein said polysilicon segment is a floating gate of a memory cell in said memory region.

3. The method of claim 1, wherein said lower dielectric segment in said memory region is a floating gate dielectric of a memory cell in said memory region.

4. The method of claim 1, wherein said first high-k segment is a transistor gate dielectric of a logic field-effect transistor (FET), and said first metal segment is a metal gate of said logic FET.

5. The method of claim 1 further comprising forming a source/drain region adjacent to said polysilicon segment in said memory region and adjacent to said sacrificial polysilicon segment in said logic region.

6. The method of claim 1 further comprising forming a cap segment over said polysilicon segment in said memory region and over said sacrificial polysilicon segment in said logic region, wherein

the cap prevents silicidation of said polysilicon segment and said sacrificial polysilicon segment.

7. The method of claim 1 wherein said second metal segment in said memory region is a control gate of said memory cell.

8. The method of claim 1, wherein said second high-k segment in said memory region is a control gate dielectric of a memory cell in said memory region.

9. The method of claim 1, wherein said polysilicon segment is in contact with the second high-k segment.

10. The method of claim 1, wherein the first high-k segment includes a first part that is between the first spacer and the first metal segment and a second part that is between the first metal segment and the common substrate.

11. A semiconductor die, comprising:

a common substrate including a logic region and a memory region;

a logic field-effect transistor (FET) in said logic region, said logic FET having a first spacer and a metal gate that is over a transistor gate dielectric segment on said common substrate in a stacking direction, wherein

said logic FET is formed by a sacrificial polysilicon segment and a lower dielectric segment having been removed from said logic region,

said metal gate and a first metal segment are formed from a metal layer,

said transistor gate dielectric segment and a first high-k segment are formed from a high-k layer, and

said first spacer is adjacent to said sacrificial polysilicon segment and said first high-k segment in a first direction that is perpendicular to the stacking direction; and

a memory cell in said memory region, said memory cell having a polysilicon segment formed over a lower dielectric segment on said common substrate, a second high-k segment over the polysilicon segment, a second metal segment over the second high-k segment and a second spacer that are adjacent to said polysilicon segment and said second high-k segment in said first direction, wherein

the logic FET in the logic region and the memory cell in the memory region are concurrently fabricated upon the common substrate.

12. The semiconductor die of claim 11, wherein said polysilicon segment is a floating gate of said memory cell, and said second metal segment is a control gate of said memory cell.

13. The semiconductor die of claim 11, wherein said lower dielectric segment is a floating gate dielectric of said memory cell.

14. The semiconductor die of claim 11, wherein said second high-k segment is a control gate dielectric of said memory cell.

15. The semiconductor die of claim 11, wherein said lower dielectric segment comprises an oxide.

16. The semiconductor die of claim 11, where said high-k segment is selected from the group consisting of hafnium oxide (HfO₂), zirconium oxide (ZrO₂), and chromium oxide (CrO₂).

17. The semiconductor die of claim 11, wherein said metal layer is selected from the group consisting of tantalum (Ta), tantalum nitride (TaN), and titanium nitride (TiN).

18. The semiconductor die of claim 11, wherein said memory cell and said logic FET are within an interlayer dielectric, said interlayer dielectric comprising a nitride.

19. The semiconductor die of claim 11, wherein said memory cell and said logic FET each comprises a source/drain region and a silicide segment formed on said source/drain region.

20. A semiconductor die, comprising:

a substrate including a logic region and a memory region;

a logic field-effect transistor (FET) in said logic region, said logic FET including a first high-k segment over the substrate in a stacking direction, and a first metal segment over the first high-k segment in the stacking direction, and a first spacer that is adjacent to said first high-k segment in a first direction that is perpendicular to the stacking direction; and

a memory cell in said memory region, said memory cell including a lower dielectric segment over said substrate in the stacking direction, a polysilicon segment over said lower dielectric segment in the stacking direction, a second high-k segment over the polysilicon segment in the stacking direction, a second metal segment over the second high-k segment in the stacking direction, and a second spacer that is adjacent to said polysilicon segment and said second high-k segment in the first direction.