Semiconductor package including antenna layer and manufacturing method thereof

• US 9,129,954 B2
• Filed: 03/07/2013
• Issued: 09/08/2015
• Est. Priority Date: 03/07/2013
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Yen, Han-Chee, Chen, Shih-Yuan, Lai, Chien-Pai, Cheng, Ming-Hsien
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US13/789,382
• Publication Number:
  US 20140252595A1
• Time in Patent Office: 915 Days
• Field of Search: 257/737, 257/692, 257/E21.508, 257/E21.505, 257/E23.01, 257/E21.332, 257/704, 257/788, 438/122, 438/127
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73259 Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/1531 the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01Q 1/2283 : mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
• CPC Class Codes: H01Q 11/04 : with parts bent, folded, shaped, screened or electrically loaded to obtain desired phase relation of radiation from selected sections of the antenna H01Q11/06 – H01Q11/10 take precedence
• CPC Class Codes: H01Q 9/0407 : Substantially flat resonant element parallel to ground plane, e.g. patch antenna dipole H01Q9/285; monopole H01Q9/40

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor chip, a package body and an antenna layer. The semiconductor chip is disposed on the substrate. The package body encapsulates the semiconductor chip and includes an upper surface. The antenna layer is formed on the upper surface of the package body and includes two antenna slot groups connected together. Each antenna slot group includes a wave guiding slot extending along a first direction, and an irradiation slot group extending along a second direction, wherein the irradiation slot group is connected to the wave guiding slot.

Claims

1. A semiconductor package comprising:

a substrate;

a semiconductor chip disposed on the substrate;

a package body encapsulating the semiconductor chip and including an upper surface;

an antenna layer formed on the upper surface of the package body, the antenna layer including two antenna slot groups connected together, wherein each antenna slot group includes a first wave guiding slot extending along a first direction, and a first irradiation slot group extending along a second direction, wherein the first irradiation slot group is connected to the first wave guiding slot.

2. The semiconductor package of claim 1, wherein the first irradiation slot group includes at least two irradiation slots.

3. The semiconductor package of claim 1, wherein the antenna layer further includes an impedance matching slot connecting the two antenna slot groups.

4. The semiconductor package of claim 1, wherein each antenna slot group further includes:

a second wave guiding slot that extends along the first direction, wherein the first irradiation slot group is connected to the second wave guiding slot; and

a second irradiation slot group connected to the second wave guiding slot and extending along the second direction.

5. The semiconductor package of claim 1, further comprising:

a feeding element electrically connected to the semiconductor chip and located between the two antenna slot groups.

6. The semiconductor package of claim 5, wherein the substrate includes a grounding segment, the antenna layer includes a feeding layer and an irradiation layer, the feeding element is electrically connected to the feeding layer, and the irradiation layer is electrically connected to the grounding segment and separated from the feeding layer.

7. The semiconductor package of claim 6, wherein the package body includes a plurality of through holes surrounding the feeding element, the semiconductor package further comprising:

a plurality of conductive pillars formed within the through holes and electrically connected to the grounding segment.

8. The semiconductor package of claim 5, wherein the feeding element is disposed on and in contact with an upper surface of the semiconductor chip.

9. The semiconductor package of claim 1, wherein the antenna layer extends to a lateral surface of the package body.

10. A semiconductor package, comprising:

a substrate;

a semiconductor chip disposed on the substrate;

a first package body encapsulating the semiconductor chip;

a second package body covering the first package body; and

an antenna layer formed on the second package body, the antenna layer including two antenna slot groups, wherein each antenna slot group includes;

a wave guiding slot; and

an irradiation slot group connected to the wave guiding slot.

11. The semiconductor package of claim 10, wherein the first package body includes an upper surface, further comprising:

a shielding layer formed on the upper surface of the first package body, wherein the shielding layer is covered by the second package body.

12. The semiconductor package of claim 11, further comprising:

a feeding element including a first portion and a second portion, wherein the first portion electrically connects the shielding layer and the semiconductor chip; and

the second portion electrically connects the shielding layer and the antenna layer.

13. The semiconductor package of claim 10, further comprising:

a feeding element;

a plurality of through holes in the second package body surrounding the feeding element; and

a plurality of conductive pillars formed within the through holes and electrically connected to the antenna layer.

14. The semiconductor package of claim 10, further comprising a shielding layer formed on a lateral surface of the first package body.

15. The semiconductor package of claim 14, further comprising:

a feeding element including a first portion and a second portion, wherein the first portion is electrically connected to the semiconductor chip through the first package body; and

the second portion is electrically connected to the shielding layer and the antenna layer.

16. A semiconductor package comprising:

a substrate;

a semiconductor chip disposed on the substrate;

a package body encapsulating the semiconductor chip and including an upper surface;

an antenna layer formed on the upper surface of the package body, the antenna layer including two antenna slot groups connected together, wherein each antenna slot group includes at least one wave guiding slot extending along a first direction, and at least one irradiation slot group extending along a second direction, wherein each of the at least one irradiation slot group is connected to at least one of the at least one wave guiding slot.

17. The semiconductor package of claim 16, wherein the at least one wave guiding slot in a first of the two antenna slot groups comprises two wave guiding slots.

18. The semiconductor package of claim 16, wherein the at least one wave guiding slot in a first of the two antenna slot groups comprises three wave guiding slots.

19. The semiconductor package of claim 16, wherein the at least one wave guiding slot in a first of the two antenna slot groups comprises four wave guiding slots.

20. The semiconductor package of claim 16, wherein the at least one irradiation slot group in a first of the two antenna slot groups comprises two irradiation slot groups.

21. The semiconductor package of claim 16, wherein the at least one irradiation slot group in a first of the two antenna slot groups comprises three irradiation slot groups.