Schemes for forming barrier layers for copper in interconnect structures

• US 9,129,968 B2
• Filed: 04/28/2014
• Issued: 09/08/2015
• Est. Priority Date: 11/21/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chen, Hai-Ching, Bao, Tien-I
• Primary Examiner(s): Sarkar, Asok K
• Application Number:
  US14/263,842
• Publication Number:
  US 20140231999A1
• Time in Patent Office: 498 Days
• Field of Search: 257/751
• US Class Current: 1/1
• CPC Class Codes: H01L 21/322 to modify their internal properties, e.g. to produce internal imperfections
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.

Claims

1. A semiconductor device comprising:

a dielectric layer over a substrate;

a conductive wire embedded within the dielectric layer, the conductive wire comprising a conductive material;

a first barrier layer between the dielectric layer and the conductive wire; and

a capping layer over the conductive wire, the capping layer comprising the conductive material and a carbon-containing silane derivative, wherein the capping layer laterally extends beyond the conductive wire.

2. The semiconductor device of claim 1, wherein the conductive material is copper.

3. The semiconductor device of claim 1, wherein the capping layer does not extend over the dielectric layer.

4. The semiconductor device of claim 1, wherein the capping layer extends into a first region between the conductive wire and the dielectric layer, the first region being over the first barrier layer.

5. The semiconductor device of claim 1, wherein the capping layer is over the first barrier layer.

6. The semiconductor device of claim 5, wherein the dielectric layer has a first top surface that is planar with a second top surface of the conductive wire.

7. The semiconductor device of claim 1, wherein the first barrier layer comprises a material selected from the group consisting essentially of cobalt, nickel, and combinations thereof.

8. The semiconductor device of claim 1, wherein the capping layer is terminated with nitrogen-containing terminals.

9. The semiconductor device of claim 1, wherein the capping layer is terminated with carbon-containing terminals.

10. A semiconductor device comprising:

a dielectric material over a substrate;

an opening within the dielectric material;

a first barrier layer at least partially lining the opening within the dielectric material;

a conductive material adjacent to the first barrier layer; and

a capping layer over the conductive material, wherein the capping layer extends past the conductive material in a direction parallel with a major surface of the substrate and comprises the conductive material and a carbon containing silane derivative.

11. The semiconductor device of claim 10, wherein the conductive material is copper.

12. The semiconductor device of claim 10, wherein the capping layer extends over the first barrier layer and between the conductive material and the dielectric material.

13. The semiconductor device of claim 10, wherein the capping layer does not extend over the dielectric material.

14. The semiconductor device of claim 10, wherein the capping layer is over the first barrier layer.

15. A semiconductor device comprising:

a conductor over a substrate, the conductor comprising a first material;

a barrier layer adjacent to sidewalls of the conductor;

a dielectric material adjacent to the barrier layer; and

a capping layer in physical contact with the conductor, wherein the capping layer comprises the first material and a carbon-containing silane derivative, wherein the capping layer has a first width parallel with a major surface of the substrate and wherein the conductor has a second width parallel with the major surface of the substrate, the second width being less than the first width.

16. The semiconductor device of claim 15, wherein the first material is copper.

17. The semiconductor device of claim 15, wherein the capping layer extends over the barrier layer and between the first material and the dielectric material.

18. The semiconductor device of claim 15, wherein the capping layer does not extend over the dielectric material.

19. The semiconductor device of claim 15, wherein the capping layer is over the barrier layer.

20. The semiconductor device of claim 15, wherein the capping layer is terminated with nitrogen-containing terminals.