SPS receiver with adjustable linearity

• US 9,130,509 B2
• Filed: 12/12/2013
• Issued: 09/08/2015
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Xu, Yang, Pals, Timothy Paul, Wang, Kevin Hsi Huai
• Primary Examiner(s): Choe, Henry
• Application Number:
  US14/105,130
• Publication Number:
  US 20140097905A1
• Time in Patent Office: 635 Days
• Field of Search: 330/296, 330/285, 330/288
• US Class Current: 1/1
• CPC Class Codes: G01S 19/21 Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 3/04 with semiconductor devices only
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/24 of transmitter output stages
• CPC Class Codes: H04B 2001/045 with means for improving efficiency
• CPC Class Codes: H04B 7/18513 Transmission in a satellite or space-based system
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A device includes a low noise amplifier (LNA) for amplifying an input signal, with the LNA including a first transistor configured to receive the input signal, a second transistor configured to receive a bias current and forming a current mirror for the first transistor, and an operational amplifier (op amp) operative to generate a bias voltage for the first and second transistors to match operating points of the first and second transistors.

Claims

1. A device including a low noise amplifier (LNA) for amplifying an input signal, the LNA comprising:

a first transistor configured to receive the input signal,

a second transistor configured to receive a bias current and forming a current mirror for the first transistor, and

an operational amplifier (op amp) operative to generate a bias voltage for the first transistor and for the second transistor to match operating points of the first and second transistors, wherein the op amp is configured to receive a first voltage and a second voltage at inverting and non-inverting inputs, respectively, and to generate the bias voltage based on the first voltage and the second voltage, the first voltage being a replicated output voltage of the first transistor, and the second voltage being an output voltage of the second transistor.

2. The device of claim 1, wherein the LNA further comprises:

a third transistor coupled to the first transistor in a cascode configuration and configured to provide an output signal for the LNA.

3. The device of claim 2, wherein the LNA further comprises:

a fourth transistor configured to provide the replicated output voltage of the first transistor, the third and four transistors having gates coupled together.

4. The device of claim 1, wherein the LNA further comprises:

a source degeneration inductor coupled to a source of the first transistor, and

a source degeneration resistor coupled to a source of the second transistor, the source degeneration resistor modeling resistive loss of the source degeneration inductor.

5. The device of claim 1, wherein a bias current of the first transistor is multiple times the bias current received by the second transistor.

6. The device of claim 1, wherein a bias current of the first transistor is at least ten times the bias current received by the second transistor.

7. The device of claim 1, wherein the LNA further comprises:

a low-pass filter configured to receive the bias voltage from the op amp and provide a filtered bias voltage to the first transistor.

8. The device of claim 1, further comprising:

at least one bias current source configured to provide adjustable bias current for the second transistor.

9. An integrated circuit including a low noise amplifier (LNA) for amplifying an input signal, the LNA comprising:

a first transistor configured to receive the input signal;

a second transistor configured to receive a bias current and forming a current mirror for the first transistor; and

an operational amplifier (op amp) operative to generate a bias voltage for the first transistor and for the second transistor to match operating points of the first and second transistors, wherein the op amp is configured to receive a first voltage and a second voltage at inverting and non-inverting inputs, respectively, and to generate the bias voltage based on the first voltage and the second voltage, the first voltage being a replicated output voltage of the first transistor, and the second voltage being an output voltage of the second transistor.

10. The integrated circuit of claim 9, wherein the LNA further comprises:

a third transistor coupled to the first transistor in a cascode configuration and configured to provide an output signal for the LNA; and

a fourth transistor configured to provide the replicated output voltage of the first transistor, the third and four transistors having gates coupled together.