Method and apparatus for use in improving linearity of MOSFETs using an accumulated charge sink

• US 9,130,564 B2
• Filed: 03/25/2013
• Issued: 09/08/2015
• Est. Priority Date: 07/11/2005
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Brindle, Christopher N., Stuber, Michael A., Kelly, Dylan J., Kemerling, Clint L., Imthurn, George, Welstand, Robert B., Burgener, Mark L.
• Primary Examiner(s): Nguyen, Dao H
• Assistant Examiner(s): Nguyen, Tram H
• Application Number:
  US13/850,251
• Publication Number:
  US 20130293280A1
• Time in Patent Office: 897 Days
• Field of Search: 257/105, 257/40, 257/347, 257/402, 257/403, 257/61, 257/327, 257/333, 257/337, 257/346, 257/59, 257/352, 257/E29.422, 327/264, 327/272, 327/389, 327/434, 327/479, 455/333, 455/425, 455/550.1, 455/434, 455/479
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

Claims

1. An accumulated charge control (ACC) NMOSFET (ACC NMOSFET), adapted to process RF signals, and adapted to control nonlinear response of RF signals processed by the ACC NMOSFET, comprising:

a) an NMOSFET having a floating body, a gate, a source, a drain and a gate oxide layer between the gate and the body, wherein the NMOSFET is selectively biased to operate in an accumulated charge regime, and wherein, but for an accumulated charge control structure, accumulated charge accumulates within the body in a region proximate to the gate oxide when the NMOSFET is biased to operate in the accumulated charge regime; and

b) the accumulated charge control structure comprising an accumulated charge sink (ACS) coupled to the body of the NMOSFET, wherein when the NMOSFET is operated in the accumulated charge regime, an ACS bias voltage (VACS) is applied to the ACS to remove or otherwise control the accumulated charge;

wherein the VACS is sufficiently negative with respect to ground, the source, and the drain to cause removal of or otherwise control the accumulated charge.

2. The ACC NMOSFET of claim 1, wherein the NMOSFET operates in the accumulated charge regime at least when the NMOSFET is biased by means of a gate control voltage (Vg) to operate in an off-state (non-conducting state).

3. The ACC NMOSFET of claim 2, wherein no non-zero DC voltage with respect to ground is applied to either the source or the drain of the NMOSFET.

4. The ACC NMOSFET of claim 2, wherein no DC voltage with respect to ground is applied to the drain of the ACC NMOSFET.

5. The ACC NMOSFET of claim 2, wherein the VACS applied to the ACS comprises a negative bias voltage, wherein the negative bias voltage is substantially negative with respect to ground, the source and the drain.

6. The ACC NMOSFET of claim 3, wherein no DC voltage is applied between the source and the drain.

7. The ACC NMOSFET of claim 5 or 6, wherein the gate control voltage Vg and VACS are independently controlled.

8. The ACC NMOSFET of claim 1, wherein removing or otherwise controlling the accumulated charge within the body of the NMOSFET improves linearity of RF signals processed by or coupled to the ACC NMOSFET.

9. A circuit for processing RF signals, comprising:

(a) a first ACC NMOSFET in accordance with claim 1 or 2, the first ACC NMOSFET having a first floating body, a first gate, a first source, and a first drain, and a first ACS coupled to the body of the first ACC NMOSFET;

(b) a second ACC NMOSFET in accordance with claim 1 or 2, the second ACC NMOSFET having a second floating body, a second gate, a second source, a second drain, and a second ACS coupled to the body of the second ACC NMOSFET;

wherein either of the second source or second drain of the second ACC NMOSFET is coupled to either of the first source or first drain of the first ACC NMOSFET; and

wherein removing or otherwise controlling accumulated charge within the body of the first ACC NMOSFET improves linearity of RF signals processed by the circuit.

10. The circuit of claim 9, wherein the first ACC NMOSFET and the second ACC NMOSFET are coupled together via a capacitor.

11. The circuit of claim 9, wherein the first ACC NMOSFET and the second ACC NMOSFET are coupled together via a conductive interconnect material.

12. The ACC NMOSFET of claim 1 or 2, wherein the gate and the ACS are coupled together.

13. The ACC NMOSFET of claim 12, wherein the ACS and the gate are controlled by the gate control voltage Vg.

14. The ACC NMOSFET of claim 1 or 2, wherein the ACC NMOSFET has an inherent power handling capability, and wherein the ACC NMOSFET is capable of processing RF signals having increased power levels by removing or otherwise reducing the accumulated charge from the NMOSFET body.

15. The ACC NMOSFET of claim 1 or 2, wherein a diode is coupled between the gate and the ACS such that the diode prevents current flow into the body when the ACC NMOSFET is in the on-state.

16. The ACC NMOSFET of claim 1, wherein an electrical coupling means is coupled between the gate and the ACS such that the electrical coupling means prevents current flow into the body when the ACC NMOSFET is off.

17. The ACC NMOSFET of claim 1 or 2, wherein the VACS applied to the ACS comprises a negative DC bias voltage, and wherein the negative DC bias voltage is substantially more negative than the most negative value of the following:

ground, DC bias voltages applied to the source (Vs) and the drain (Vd), and a threshold voltage (Vth) of the NMOSFET.

18. The ACC NMOSFET of claim 1 or 2, wherein the VACS applied to the ACS comprises a negative DC bias voltage, and wherein the negative DC bias voltage is at least 1 Volt more negative than the most negative value of the following:

ground, bias voltages applied to the source (Vs) and the drain (Vd), and a threshold voltage (Vth) of the NMOSFET.

19. The ACC NMOSFET of claim 2, wherein when the ACC NMOSFET is biased to operate in the off-state (non-conducting state) the gate control voltage Vg is at least 1 Volt more negative than the most negative value of the following:

ground, DC bias voltages applied to the source (Vs) and the drain (Vd), and a threshold voltage (Vth) of the ACC NMOSFET.

20. The ACC NMOSFET of claim 1 or 2, further comprising an electrical contact region positioned proximate to and in electrical communication with the ACS, wherein the electrical contact region facilitates electrical coupling to the ACS.

21. The ACC NMOSFET of claim 20, wherein a second electrical contact region facilitates coupling to the body of the NMOSFET.

22. The ACC NMOSFET of claim 2 or 13, wherein the gate control voltage (Vg) comprises approximately +2.5 Volts thereby turning the NMOSFET ON.

23. The ACC NMOSFET of claim 2 or 13, wherein the gate control voltage (Vg) comprises approximately −

2.5 Volts thereby disabling the NMOSFET.

24. The ACC NMOSFET of claim 1 or 2, wherein the NMOSFET comprises a partially depleted NMOSFET.

25. The ACC NMOSFET of claim 1 or 2, wherein the NMOSFET comprises a fully depleted NMOSFET.

49. The ACC NMOSFET of claim 1 or 26, wherein the silicon layer has a thickness of between approximately 100 Angstroms to approximately 2,000 Angstroms.

50. The ACC NMOSFET of claim 1 or 26, wherein the silicon layer comprises a thin layer.

26. An accumulated charge control NMOSFET (ACC NMOSFET) adapted to switch RF signals and further adapted to control nonlinear response of RF signals switched by the ACC NMOSFET, comprising:

a) an NMOSFET including a floating body, a gate, a drain, a source, and a gate oxide layer between the gate and the body, wherein the NMOSFET has a threshold voltage (Vth); and

b) an accumulated charge sink (ACS) electrically coupled to the body of the NMOSFET, wherein the NMOSFET operates in an accumulated charge regime when the NMOSFET is biased by means of a gate control voltage (Vg) to operate in an off-state (non-conducting state), and wherein, but for the ACS, charge accumulates within the body in a region proximate the gate oxide, and wherein the NMOSFET has no source-to-drain DC voltage applied thereto; and

wherein an ACS bias voltage (VACS) is applied to the ACS and thereby substantially prevents accumulated charge from accumulating in the body, and wherein VACS is sufficiently negative with respect to ground, the source, the drain, and Vth to substantially prevent accumulated charge from accumulating in the body; and

c) a silicon-on-insulator substrate having at least a silicon layer and an insulating layer;

wherein the NMOSFET and ACS are fabricated in the silicon layer to form the ACC NMOSFET and wherein the NMOSFET body is situated between the source, the drain, the gate oxide, and the insulating layer, wherein the source and drain of the MOSFET extend through an entire thickness of the silicon layer and further down to the insulating layer.

27. The ACC NMOSFET of claim 26, wherein no non-zero DC voltage with respect to ground is applied to either the source or the drain of the NMOSFET.

28. The ACC NMOSFET of claim 27, wherein the VACS applied to the ACS comprises a negative bias voltage, wherein the negative bias voltage is substantially negative with respect to ground, the source and the drain.

29. The ACC NMOSFET of claim 27, wherein no DC voltage is applied between the source and the drain.

30. The ACC NMOSFET of claim 27, wherein no DC voltage with respect to ground is applied to the drain of the NMOSFET.

31. The ACC NMOSFET of claim 28 or 29, wherein the gate control voltage Vg and VACS are independently controlled.

32. The ACC NMOSFET of claim 26, wherein preventing accumulated charge from accumulating in the body of the NMOSFET improves linearity of RF signals processed by or coupled to the ACC NMOSFET.

33. The ACC NMOSFET of claim 26 or 32, wherein the ACC NMOSFET is coupled to a second ACC NMOSFET having a second NMOSFET including a second gate, a second source and a second drain, wherein either the second source or second drain of the second NMOSFET is coupled to either the source or the drain of the NMOSFET of the ACC NMOSFET, thereby conveying applied RF signals to the second NMOSFET, and wherein preventing accumulated charge from accumulating in the body of the off-state ACC NMOSFET improves linearity of RF signals switched by the second ACC NMOSFET.

34. The ACC NMOSFET of claim 33, wherein the ACC NMOSFET and the second ACC NMOSFET are coupled together via a capacitor.

35. The ACC NMOSFET of claim 26 or 32, wherein the gate and the ACS are coupled together.

36. The ACC NMOSFET of claim 35, wherein the ACS and the gate are controlled by the gate control voltage Vg.

37. The ACC NMOSFET of claim 26 or 32, wherein the ACC NMOSFET has an inherent power handling capability, and wherein the ACC NMOSFET is capable of processing RF signals having increased power levels by preventing the accumulated charge from accumulating in the NMOSFET body.

38. The ACC NMOSFET of claim 26 or 32, wherein a diode is coupled between the gate and the ACS such that the diode prevents current flow into the body when the ACC NMOSFET is turned ON.

39. The ACC NMOSFET of claim 26 or 32, wherein an electrical coupling means is coupled between the gate and the ACS such that the electrical coupling means prevents current flow into the body when the ACC NMOSFET is turned ON.

40. The ACC NMOSFET of claim 26 or 32, wherein the VACS applied to the ACS comprises a negative bias voltage, and wherein the negative bias voltage is substantially more negative than the most negative value of the following:

ground, bias voltages applied to the source (Vs) and the drain (Vd), and the threshold voltage (Vth) of the NMOSFET.

41. The ACC NMOSFET of claim 26, or 32 wherein the VACS applied to the ACS comprises a negative bias voltage, and wherein the negative bias voltage is at least 1 Volt more negative than the most negative value of the following:

ground, bias voltages applied to the source (Vs) and the drain (Vd), and the threshold voltage (Vth) of the NMOSFET.

42. The ACC NMOSFET of claim 26 or 32, wherein when the NMOSFET is biased to operate in the off-state (non-conducting state), the gate control voltage Vg is at least 1 Volt more negative than the most negative value of the following:

ground, bias voltages applied to the source (Vs) and the drain (Vd), and the threshold voltage (Vth) of the NMOSFET.

43. The ACC NMOSFET of claim 26 or 32, further comprising an electrical contact region positioned proximate to and in electrical communication with the ACS, wherein the electrical contact region facilitates electrical coupling to the ACS.

44. The ACC NMOSFET of claim 43, wherein a second electrical contact region facilitates coupling to the body of the NMOSFET.

45. The ACC NMOSFET of claim 26 or 32, wherein the gate control voltage (Vg) comprises approximately +2.5 Volts thereby enabling the NMOSFET.

46. The ACC NMOSFET of claim 26 or 32, wherein the gate control voltage (Vg) comprises approximately −

2.5 Volts thereby disabling the NMOSFET.

47. The ACC NMOSFET of claim 26 or 32, wherein the NMOSFET comprises a partially depleted NMOSFET.

48. The ACC NMOSFET of claim 26 or 32, wherein the NMOSFET comprises a fully depleted NMOSFET.

51. An accumulated charge control (ACC) NMOSFET (ACC NMOSFET), adapted to process RF signals and to control nonlinear response of RF signals processed by the ACC NMOSFET, comprising:

a) an NMOSFET having a floating body, a gate, a source, a drain and a gate oxide layer between the gate and the body;

b) an accumulated charge sink (ACS) coupled to the body of the NMOSFET;

wherein the NMOSFET is selectively biased to operate in an accumulated charge regime, and when so biased;

(1) but for the ACS, accumulated charge accumulates within the body in a region proximate to the gate oxide; and

(2) an ACS bias voltage (VACS) is applied to the ACS to remove or otherwise control the accumulated charge, wherein the VACS is sufficiently negative with respect to ground, the source, and the drain to cause removal of or otherwise control the accumulated charge;

and

c) a silicon-on-insulator substrate having at least a silicon layer and an insulating layer;

wherein the source and drain of the NMOSFET extend through an entire thickness of the silicon layer and further down to the insulating layer.